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Searched refs:SrcVT (Results 1 – 25 of 42) sorted by relevance

12

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp168 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
825 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
827 if (SrcVT == MVT::i1 && Subtarget->useCRBits()) in PPCEmitCmp()
841 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
842 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
867 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
957 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in SelectFPExt() local
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsFastISel.cpp187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
997 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
1000 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1076 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1079 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
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DMipsMSAInstrInfo.td3608 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3610 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3611 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3665 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3668 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3669 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3673 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3676 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3677 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3681 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
231 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
256 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
259 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
262 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1160 MVT SrcVT = RetVT; in emitAddSub() local
1186 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2812 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2813 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
[all …]
DAArch64ISelLowering.cpp3280 EVT SrcVT = SrcVal.getValueType(); in LowerFP_ROUND() local
3282 if (useSVEForFixedLengthVectorVT(SrcVT)) in LowerFP_ROUND()
3285 if (SrcVT != MVT::f128) { in LowerFP_ROUND()
3287 if (useSVEForFixedLengthVectorVT(SrcVT)) in LowerFP_ROUND()
3381 EVT SrcVT = SrcVal.getValueType(); in LowerFP_TO_INT_SAT() local
3390 if (SrcVT.isVector()) in LowerFP_TO_INT_SAT()
3398 if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16()) in LowerFP_TO_INT_SAT()
3404 if ((SrcVT == MVT::f64 || SrcVT == MVT::f32 || in LowerFP_TO_INT_SAT()
3405 (SrcVT == MVT::f16 && Subtarget->hasFullFP16())) && in LowerFP_TO_INT_SAT()
6998 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN() local
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DAArch64ISelDAGToDAG.cpp587 EVT SrcVT; in getExtendTypeForNode() local
589 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
591 SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode()
593 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
595 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
597 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
599 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
604 EVT SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode() local
605 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
607 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp999 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1000 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
1004 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1005 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 && in ExpandANY_EXTEND_VECTOR_INREG()
1007 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits(); in ExpandANY_EXTEND_VECTOR_INREG()
1008 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandANY_EXTEND_VECTOR_INREG()
1010 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1026 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
1033 EVT SrcVT = Src.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1043 unsigned SrcEltWidth = SrcVT.getScalarSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
[all …]
DTargetLowering.cpp653 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
655 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
658 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
666 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 && in SimplifyMultipleUseDemandedBits()
669 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in SimplifyMultipleUseDemandedBits()
692 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
802 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
804 if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
806 DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) { in SimplifyMultipleUseDemandedBits()
1873 EVT SrcVT = Src.getValueType(); in SimplifyDemandedBits() local
[all …]
DLegalizeDAG.cpp725 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
726 TypeSize SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
730 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
738 (SrcVT != MVT::i1 || in LegalizeLoadOps()
743 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
763 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
768 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
774 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
851 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
879 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
[all …]
DFastISel.cpp1375 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1378 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1388 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1396 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1423 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1431 if (SrcVT == DstVT) { in selectBitCast()
1432 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1444 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1798 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1800 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
DLegalizeFloatTypes.cpp927 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted, in findFPToIntLibcall() argument
936 LC = Signed ? RTLIB::getFPTOSINT(SrcVT, Promoted) in findFPToIntLibcall()
937 : RTLIB::getFPTOUINT(SrcVT, Promoted); in findFPToIntLibcall()
1649 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1662 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1674 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1678 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1694 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1706 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1714 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
[all …]
DLegalizeVectorTypes.cpp538 EVT SrcVT = Src.getValueType(); in ScalarizeVecRes_FP_TO_XINT_SAT() local
542 if (getTypeAction(SrcVT) == TargetLowering::TypeScalarizeVector) in ScalarizeVecRes_FP_TO_XINT_SAT()
546 ISD::EXTRACT_VECTOR_ELT, dl, SrcVT.getVectorElementType(), Src, in ScalarizeVecRes_FP_TO_XINT_SAT()
1940 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp() local
1958 if (SrcVT.getVectorElementCount().isKnownEven() && in SplitVecRes_ExtendOp()
1959 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
1961 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx); in SplitVecRes_ExtendOp()
1962 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx); in SplitVecRes_ExtendOp()
1966 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) && in SplitVecRes_ExtendOp()
2121 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_FP_TO_XINT_SAT() local
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMFastISel.cpp201 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1339 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1355 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1356 SrcVT == MVT::i1) { in ARMEmitCmp()
1370 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1378 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1420 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1534 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1535 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
[all …]
DARMISelLowering.h453 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
616 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86FastISel.cpp95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
708 unsigned Src, EVT SrcVT, in X86FastEmitExtend() argument
710 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1244 EVT SrcVT = TLI.getValueType(DL, RV->getType()); in X86SelectRet() local
1247 if (SrcVT != DstVT) { in X86SelectRet()
1248 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1256 if (SrcVT == MVT::i1) { in X86SelectRet()
1261 SrcVT = MVT::i8; in X86SelectRet()
1266 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1552 MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); in X86SelectZExt() local
[all …]
DX86ISelLowering.cpp5326 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
5334 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
6784 EVT SrcVT = Op.getOperand(0).getValueType(); in getTargetConstantBitsFromNode() local
6785 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in getTargetConstantBitsFromNode()
7724 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask() local
7725 if (!SrcVT.getScalarType().isByteSized()) in getFauxShuffleMask()
7728 unsigned SrcByte = SrcIdx * (SrcVT.getScalarSizeInBits() / 8); in getFauxShuffleMask()
7731 std::min<unsigned>(MinBitsPerElt, SrcVT.getScalarSizeInBits()); in getFauxShuffleMask()
7812 EVT SrcVT = Src.getValueType(); in getFauxShuffleMask() local
7814 if (!SrcVT.isSimple() || (SrcVT.getSizeInBits() % 128) != 0 || in getFauxShuffleMask()
[all …]
DX86SelectionDAGInfo.cpp280 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
284 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
DX86ISelLowering.h1302 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1376 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp966 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable() argument
973 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
1420 EVT SrcVT = Op.getOperand(0).getValueType(); in LowerEXTRACT_SUBVECTOR() local
1423 if (((SrcVT == MVT::v4f16 && VT == MVT::v2f16) || in LowerEXTRACT_SUBVECTOR()
1424 (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) && in LowerEXTRACT_SUBVECTOR()
2567 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
2569 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
2579 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerUINT_TO_FP()
2604 EVT SrcVT = Src.getValueType(); in LowerSINT_TO_FP() local
2606 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
[all …]
DSIInstrInfo.td264 class isFloatType<ValueType SrcVT> {
265 bit ret = !or(!eq(SrcVT.Value, f16.Value),
266 !eq(SrcVT.Value, f32.Value),
267 !eq(SrcVT.Value, f64.Value),
268 !eq(SrcVT.Value, v2f16.Value),
269 !eq(SrcVT.Value, v4f16.Value),
270 !eq(SrcVT.Value, v2f32.Value),
271 !eq(SrcVT.Value, v2f64.Value),
272 !eq(SrcVT.Value, v4f64.Value));
275 class isIntType<ValueType SrcVT> {
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTypePromotion.cpp972 EVT SrcVT = TLI->getValueType(DL, I->getType()); in runOnFunction() local
973 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in runOnFunction()
976 if (TLI->getTypeAction(ICmp->getContext(), SrcVT) != in runOnFunction()
979 EVT PromotedVT = TLI->getTypeToTransformTo(ICmp->getContext(), SrcVT); in runOnFunction()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
DScalarizer.cpp701 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); in visitBitCastInst() local
702 if (!DstVT || !SrcVT) in visitBitCastInst()
706 unsigned SrcNumElems = cast<FixedVectorType>(SrcVT)->getNumElements(); in visitBitCastInst()
738 auto *MidTy = FixedVectorType::get(SrcVT->getElementType(), FanIn); in visitBitCastInst()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.h306 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
308 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
DRISCVISelLowering.cpp962 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree() argument
963 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || in isTruncateFree()
964 !SrcVT.isInteger() || !DstVT.isInteger()) in isTruncateFree()
966 unsigned SrcBits = SrcVT.getSizeInBits(); in isTruncateFree()
985 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt() argument
986 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
2215 MVT SrcVT = Src.getSimpleValueType(); in LowerOperation() local
2216 MVT SrcEltVT = SrcVT.getVectorElementType(); in LowerOperation()
2223 MVT ContainerVT = SrcVT; in LowerOperation()
2224 if (SrcVT.isFixedLengthVector()) { in LowerOperation()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetLowering.h2679 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2680 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2689 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2690 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2692 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
2769 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument

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