196   bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
231   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
256   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
259   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
262   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1160   MVT SrcVT = RetVT;  in emitAddSub()  local
1186     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);  in emitAddSub()
1275     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);  in emitAddSub()
2812   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectFPToInt()  local
2813   if (SrcVT == MVT::f128 || SrcVT == MVT::f16)  in selectFPToInt()
2817   if (SrcVT == MVT::f64) {  in selectFPToInt()
2851   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectIntToFP()  local
2854   if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {  in selectIntToFP()
2856         emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);  in selectIntToFP()
2862   if (SrcVT == MVT::i64) {  in selectIntToFP()
3022       MVT SrcVT = ArgVT;  in processCallArgs()  local
3023       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3032       MVT SrcVT = ArgVT;  in processCallArgs()  local
3033       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3872   MVT SrcVT = SrcEVT.getSimpleVT();  in selectTrunc()  local
3875   if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&  in selectTrunc()
3876       SrcVT != MVT::i8)  in selectTrunc()
3892   if (SrcVT == MVT::i64) {  in selectTrunc()
4016 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSL_ri()  argument
4018   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSL_ri()
4020   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSL_ri()
4021           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSL_ri()
4029   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSL_ri()
4035     if (RetVT == SrcVT) {  in emitLSL_ri()
4042       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSL_ri()
4082   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSL_ri()
4119 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSR_ri()  argument
4121   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSR_ri()
4123   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSR_ri()
4124           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSR_ri()
4132   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4138     if (RetVT == SrcVT) {  in emitLSR_ri()
4145       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4183     Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4186     SrcVT = RetVT;  in emitLSR_ri()
4187     SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4198   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSR_ri()
4235 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitASR_ri()  argument
4237   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitASR_ri()
4239   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitASR_ri()
4240           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitASR_ri()
4248   unsigned SrcBits = SrcVT.getSizeInBits();  in emitASR_ri()
4254     if (RetVT == SrcVT) {  in emitASR_ri()
4261       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitASR_ri()
4303   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitASR_ri()
4315 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4325       ((SrcVT !=  MVT::i1) && (SrcVT !=  MVT::i8) &&  in emitIntExt()
4326        (SrcVT !=  MVT::i16) && (SrcVT !=  MVT::i32)))  in emitIntExt()
4332   switch (SrcVT.SimpleTy) {  in emitIntExt()
4425                                          MVT SrcVT) {  in optimizeIntExtLoad()  argument
4453   if (RetVT != MVT::i64 || SrcVT > MVT::i32) {  in optimizeIntExtLoad()
4482   MVT SrcVT;  in selectIntExt()  local
4486   if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))  in selectIntExt()
4490   if (optimizeIntExtLoad(I, RetVT, SrcVT))  in selectIntExt()
4501       if (RetVT == MVT::i64 && SrcVT != MVT::i64) {  in selectIntExt()
4516   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()
4583       MVT SrcVT = VT;  in selectMul()  local
4589             SrcVT = VT;  in selectMul()
4598             SrcVT = VT;  in selectMul()
4610           emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);  in selectMul()
4646     MVT SrcVT = RetVT;  in selectShift()  local
4653           SrcVT = TmpVT;  in selectShift()
4662           SrcVT = TmpVT;  in selectShift()
4676       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4679       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4682       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4722   MVT RetVT, SrcVT;  in selectBitCast()  local
4724   if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))  in selectBitCast()
4730   if (RetVT == MVT::f32 && SrcVT == MVT::i32)  in selectBitCast()
4732   else if (RetVT == MVT::f64 && SrcVT == MVT::i64)  in selectBitCast()
4734   else if (RetVT == MVT::i32 && SrcVT == MVT::f32)  in selectBitCast()
4736   else if (RetVT == MVT::i64 && SrcVT == MVT::f64)  in selectBitCast()