Searched refs:Src0Reg (Results 1 – 9 of 9) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4546 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4547 if (!Src0Reg) in selectRem()
4556 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, Src1Reg); in selectRem()
4560 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg); in selectRem()
4605 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4606 if (!Src0Reg) in selectMul()
4610 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4618 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4619 if (!Src0Reg) in selectMul()
4626 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); in selectMul()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 270 unsigned Src0Reg,
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| D | AMDGPUInstructionSelector.cpp | 423 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
444 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE()
703 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
730 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
744 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT()
750 .addReg(Src0Reg) in selectG_INSERT()
939 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
944 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC()
2836 Register Src0Reg = MI.getOperand(1).getReg(); in selectG_SHUFFLE_VECTOR() local
2841 if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16) in selectG_SHUFFLE_VECTOR()
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| D | R600InstrInfo.cpp | 1219 unsigned Src0Reg, in buildDefaultInstruction() argument
1232 .addReg(Src0Reg) // $src0 in buildDefaultInstruction()
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| D | AMDGPULegalizerInfo.cpp | 1983 Register Src0Reg = MI.getOperand(1).getReg(); in legalizeFrem() local
1988 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags); in legalizeFrem()
1991 B.buildFMA(DstReg, Neg, Src1Reg, Src0Reg, Flags); in legalizeFrem()
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| D | AMDGPURegisterBankInfo.cpp | 4105 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
4107 unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits(); in getInstrMapping()
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| D | SIInstrInfo.cpp | 4885 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
4897 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); in legalizeOperandsVOP2()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1938 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
1940 if (!Src0Reg || !Src1Reg) in selectDivRem()
1943 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3652 Register Src0Reg = MI.getOperand(2).getReg(); in fewerElementsVectorCmp() local
3654 LLT SrcTy = MRI.getType(Src0Reg); in fewerElementsVectorCmp()
6561 Register Src0Reg = MI.getOperand(1).getReg(); in lowerMergeValues() local
6563 LLT SrcTy = MRI.getType(Src0Reg); in lowerMergeValues()
6567 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues()
6696 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local
6698 LLT Src0Ty = MRI.getType(Src0Reg); in lowerShuffleVector()
6714 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; in lowerShuffleVector()
6733 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); in lowerShuffleVector()
6736 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector()
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