423   Register Src0Reg = I.getOperand(2).getReg();  in selectG_UADDO_USUBO_UADDE_USUBE()  local
444       !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) ||  in selectG_UADDO_USUBO_UADDE_USUBE()
703   Register Src0Reg = I.getOperand(1).getReg();  in selectG_INSERT()  local
730   const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI);  in selectG_INSERT()
744       !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) ||  in selectG_INSERT()
750     .addReg(Src0Reg)  in selectG_INSERT()
939     Register Src0Reg = I.getOperand(2).getReg();  in selectG_INTRINSIC()  local
944     for (Register Reg : { DstReg, Src0Reg, Src1Reg })  in selectG_INTRINSIC()
2836   Register Src0Reg = MI.getOperand(1).getReg();  in selectG_SHUFFLE_VECTOR()  local
2841   if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16)  in selectG_SHUFFLE_VECTOR()
2868   Register SrcVec = normalizeVOP3PMask(Mask, Src0Reg, Src1Reg, ShufMask);  in selectG_SHUFFLE_VECTOR()