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Searched refs:RegVT (Results 1 – 21 of 21) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DCallingConvLower.cpp254 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
256 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
258 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
261 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp322 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
323 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
327 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
335 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
340 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
343 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DSwitchLoweringUtils.h213 MVT RegVT; member
227 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.cpp1159 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1161 if (RegVT == MVT::i8) { in LowerFormalArguments()
1163 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1170 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1187 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1192 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1291 EVT RegVT = VA.getLocVT(); in LowerCall() local
1301 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1304 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1307 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/
DARCISelLowering.cpp484 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
485 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
488 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
494 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp642 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
643 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
648 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
655 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/
DM68kISelLowering.cpp592 EVT RegVT = VA.getLocVT(); in LowerCall() local
603 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
606 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
609 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
612 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
893 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
895 if (RegVT == MVT::i32) in LowerFormalArguments()
901 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
907 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
910 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp844 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
846 RegVT = VA.getValVT(); in LowerFormalArguments()
848 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
850 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
856 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
857 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
858 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
859 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
863 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
865 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp2775 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2776 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2814 MVT VT = BB.RegVT; in visitBitTestCase()
8291 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in GetRegistersForValue() local
8293 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in GetRegistersForValue()
8307 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in GetRegistersForValue()
8313 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in GetRegistersForValue()
8314 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
8318 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
8335 ValueVT = RegVT; in GetRegistersForValue()
[all …]
DTargetLowering.cpp7424 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
7425 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
7522 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
7524 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
7528 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
7544 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), in expandUnalignedLoad()
7562 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
7672 MVT RegVT = getRegisterType( in expandUnalignedStore() local
7677 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
7681 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore()
[all …]
DLegalizeIntegerTypes.cpp1427 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
1433 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1449 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1301 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1302 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1307 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
1314 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCallLowering.cpp890 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); in getReturnInfo() local
891 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); in getReturnInfo()
DIRTranslator.cpp1021 B.RegVT = getMVTForLLT(MaskTy); in emitBitTestHeader()
1053 LLT SwitchTy = getLLTForMVT(BB.RegVT); in emitBitTestCase()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsISelLowering.cpp3671 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3673 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3678 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3685 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3686 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3687 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3689 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3695 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp696 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
703 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
707 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
711 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
741 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
747 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
751 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS; in tryTLSXFormLoad()
755 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS; in tryTLSXFormLoad()
DPPCISelLowering.cpp5372 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5376 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5382 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5384 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5389 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5391 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5424 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5447 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5450 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff); in buildCallOperands()
5457 RegVT)); in buildCallOperands()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp3653 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3665 if (RegVT == MVT::i8) in LowerFormalArguments()
3667 else if (RegVT == MVT::i16) in LowerFormalArguments()
3669 else if (RegVT == MVT::i32) in LowerFormalArguments()
3671 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
3673 else if (RegVT == MVT::f32) in LowerFormalArguments()
3675 else if (RegVT == MVT::f64) in LowerFormalArguments()
3677 else if (RegVT == MVT::f80) in LowerFormalArguments()
3679 else if (RegVT == MVT::f128) in LowerFormalArguments()
3681 else if (RegVT.is512BitVector()) in LowerFormalArguments()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.cpp2988 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
2993 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) { in IsEligibleForTailCallOptimization()
3002 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
4435 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4463 if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
4465 else if (RegVT == MVT::f32) in LowerFormalArguments()
4467 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 || in LowerFormalArguments()
4468 RegVT == MVT::v4bf16) in LowerFormalArguments()
4470 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 || in LowerFormalArguments()
4471 RegVT == MVT::v8bf16) in LowerFormalArguments()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5152 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
5155 if (RegVT == MVT::i32) in LowerFormalArguments()
5157 else if (RegVT == MVT::i64) in LowerFormalArguments()
5159 else if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
5161 else if (RegVT == MVT::f32) in LowerFormalArguments()
5163 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
5165 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
5167 else if (RegVT.isScalableVector() && in LowerFormalArguments()
5168 RegVT.getVectorElementType() == MVT::i1) in LowerFormalArguments()
5170 else if (RegVT.isScalableVector()) in LowerFormalArguments()
[all …]