3653       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
3665         if (RegVT == MVT::i8)  in LowerFormalArguments()
3667         else if (RegVT == MVT::i16)  in LowerFormalArguments()
3669         else if (RegVT == MVT::i32)  in LowerFormalArguments()
3671         else if (Is64Bit && RegVT == MVT::i64)  in LowerFormalArguments()
3673         else if (RegVT == MVT::f32)  in LowerFormalArguments()
3675         else if (RegVT == MVT::f64)  in LowerFormalArguments()
3677         else if (RegVT == MVT::f80)  in LowerFormalArguments()
3679         else if (RegVT == MVT::f128)  in LowerFormalArguments()
3681         else if (RegVT.is512BitVector())  in LowerFormalArguments()
3683         else if (RegVT.is256BitVector())  in LowerFormalArguments()
3685         else if (RegVT.is128BitVector())  in LowerFormalArguments()
3687         else if (RegVT == MVT::x86mmx)  in LowerFormalArguments()
3689         else if (RegVT == MVT::v1i1)  in LowerFormalArguments()
3691         else if (RegVT == MVT::v8i1)  in LowerFormalArguments()
3693         else if (RegVT == MVT::v16i1)  in LowerFormalArguments()
3695         else if (RegVT == MVT::v32i1)  in LowerFormalArguments()
3697         else if (RegVT == MVT::v64i1)  in LowerFormalArguments()
3703         ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);  in LowerFormalArguments()
3710         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,  in LowerFormalArguments()
3713         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,  in LowerFormalArguments()
3720         if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)  in LowerFormalArguments()
3727           ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);  in LowerFormalArguments()
4079     EVT RegVT = VA.getLocVT();  in LowerCall()  local
4088       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);  in LowerCall()
4091       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);  in LowerCall()
4096         Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);  in LowerCall()
4097       else if (RegVT.is128BitVector()) {  in LowerCall()
4103         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);  in LowerCall()
4106       Arg = DAG.getBitcast(RegVT, Arg);  in LowerCall()
24468   MVT RegVT = Op.getSimpleValueType();  in LowerLoad()  local
24469   assert(RegVT.isVector() && "We only custom lower vector loads.");  in LowerLoad()
24470   assert(RegVT.isInteger() &&  in LowerLoad()
24477   if (RegVT.getVectorElementType() == MVT::i1) {  in LowerLoad()
24478     assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load");  in LowerLoad()
24479     assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT");  in LowerLoad()
24491     Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT,  in LowerLoad()
45760   EVT RegVT = Ld->getValueType(0);  in combineLoad()  local
45770   if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&  in combineLoad()
45774        (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,  in combineLoad()
45777     unsigned NumElems = RegVT.getVectorNumElements();  in combineLoad()
45798     SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2);  in combineLoad()
45804   if (Ext == ISD::NON_EXTLOAD && !Subtarget.hasAVX512() && RegVT.isVector() &&  in combineLoad()
45805       RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) {  in combineLoad()
45806     unsigned NumElts = RegVT.getVectorNumElements();  in combineLoad()
45813       SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);  in combineLoad()
45821       (RegVT.is128BitVector() || RegVT.is256BitVector())) {  in combineLoad()
45832               RegVT.getFixedSizeInBits()) {  in combineLoad()
45834                                            RegVT.getSizeInBits());  in combineLoad()
45835         Extract = DAG.getBitcast(RegVT, Extract);  in combineLoad()
45849       return DAG.getLoad(RegVT, dl, Ld->getChain(), Cast, Ld->getPointerInfo(),  in combineLoad()