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Searched refs:R600 (Results 1 – 25 of 30) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.cpp26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
27 R600::sub4, R600::sub5, R600::sub6, R600::sub7, in getSubRegFromChannel()
28 R600::sub8, R600::sub9, R600::sub10, R600::sub11, in getSubRegFromChannel()
29 R600::sub12, R600::sub13, R600::sub14, R600::sub15 in getSubRegFromChannel()
42 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
47 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
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DR600InstrInfo.cpp43 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
44 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
45 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
46 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
48 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
49 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
50 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
51 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
58 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
65 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
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DR600ControlFlowFinalizer.cpp66 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
75 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
76 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
77 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
78 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
139 case R600::CF_PUSH_EG: in pushBranch()
140 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
211 case R600::KILL: in IsTrivialInst()
212 case R600::RETURN: in IsTrivialInst()
224 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
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DR600ExpandSpecialInstrs.cpp86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
90 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
91 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
93 R600::OpName::pred_sel); in runOnMachineFunction()
95 R600::OpName::pred_sel); in runOnMachineFunction()
104 case R600::PRED_X: { in runOnMachineFunction()
112 R600::ZERO); // src1 in runOnMachineFunction()
115 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
117 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
122 case R600::DOT_4: { in runOnMachineFunction()
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DR600EmitClauseMarkers.cpp38 case R600::INTERP_PAIR_XY: in OccupiedDwords()
39 case R600::INTERP_PAIR_ZW: in OccupiedDwords()
40 case R600::INTERP_VEC_LOAD: in OccupiedDwords()
41 case R600::DOT_4: in OccupiedDwords()
43 case R600::KILL: in OccupiedDwords()
63 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
75 case R600::PRED_X: in isALU()
76 case R600::INTERP_PAIR_XY: in isALU()
77 case R600::INTERP_PAIR_ZW: in isALU()
78 case R600::INTERP_VEC_LOAD: in isALU()
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DR600MachineScheduler.cpp159 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
178 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
221 case R600::PRED_X: in getAluKind()
223 case R600::INTERP_PAIR_XY: in getAluKind()
224 case R600::INTERP_PAIR_ZW: in getAluKind()
225 case R600::INTERP_VEC_LOAD: in getAluKind()
226 case R600::DOT_4: in getAluKind()
228 case R600::COPY: in getAluKind()
244 MI->getOpcode() == R600::GROUP_BARRIER) { in getAluKind()
255 case R600::sub0: in getAluKind()
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DR600ClauseMergePass.cpp27 case R600::CF_ALU: in isCFAlu()
28 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu()
78 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
85 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
91 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
110 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
118 if (RootCFAlu.getOpcode() == R600::CF_ALU_PUSH_BEFORE) in mergeIfPossible()
122 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
124 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
126 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
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DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
90 Result[Dst] = R600::PS; in getPreviousVector()
93 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
94 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
95 Result[Dst] = R600::PV_X; in getPreviousVector()
98 if (Dst == R600::OQAP) { in getPreviousVector()
104 PVReg = R600::PV_X; in getPreviousVector()
107 PVReg = R600::PV_Y; in getPreviousVector()
110 PVReg = R600::PV_Z; in getPreviousVector()
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DR600ISelLowering.cpp31 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
32 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
260 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
276 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
282 MI.getOpcode() == R600::LDS_CMPST_RET) in EmitInstrWithCustomInserter()
286 TII->get(R600::getLDSNoRetOp(MI.getOpcode()))); in EmitInstrWithCustomInserter()
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DAMDILCFGStructurizer.cpp410 if (I->getOpcode() == R600::PRED_X) { in reversePredicateSetter()
412 case R600::PRED_SETE_INT: in reversePredicateSetter()
413 I->getOperand(2).setImm(R600::PRED_SETNE_INT); in reversePredicateSetter()
415 case R600::PRED_SETNE_INT: in reversePredicateSetter()
416 I->getOperand(2).setImm(R600::PRED_SETE_INT); in reversePredicateSetter()
418 case R600::PRED_SETE: in reversePredicateSetter()
419 I->getOperand(2).setImm(R600::PRED_SETNE); in reversePredicateSetter()
421 case R600::PRED_SETNE: in reversePredicateSetter()
422 I->getOperand(2).setImm(R600::PRED_SETE); in reversePredicateSetter()
491 case R600::JUMP_COND: in getBranchNzeroOpcode()
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DR600.td1 //===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//
16 def R600 : Target {
21 let Namespace = "R600" in {
44 // Calling convention for R600
DR600OptimizeVectorRegisters.cpp56 assert(MI->getOpcode() == R600::REG_SEQUENCE); in RegSeqInfo()
141 case R600::R600_ExportSwz: in canSwizzle()
142 case R600::EG_ExportSwz: in canSwizzle()
195 Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass); in RebuildVector()
200 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG), in RebuildVector()
216 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
336 if (MI.getOpcode() != R600::REG_SEQUENCE) { in runOnMachineFunction()
DR600Processors.td1 //===-- R600Processors.td - R600 Processor definitions --------------------===//
47 def FeatureR600 : R600SubtargetFeatureGeneration<"R600", "r600",
67 // Radeon HD 2000/3000 Series (R600).
DR600Schedule.td1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
9 // R600 Instruction format definitions.
43 let Namespace = "R600";
189 XXX: R600 subtarget uses a slightly different encoding than the other
DR600Instructions.td1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
9 // TableGen definitions for instructions which are available on R600 family
16 // FIXME: Should not be arbitrarily split from other R600 inst classes.
20 let Namespace = "R600";
89 usesCustomInserter = 1, Namespace = "R600" in {
377 // R600 SDNodes
380 let Namespace = "R600" in {
443 let Namespace = "R600" in {
686 // Common Instructions R600, R700, Evergreen, Cayman
691 let Namespace = "R600", usesCustomInserter = 1 in {
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DAMDGPUSubtarget.h33 R600 = 1, enumerator
DR600AsmPrinter.cpp53 if (MI.getOpcode() == R600::KILLGT) in EmitProgramInfoR600()
DR600InstrInfo.h329 namespace R600 {
DAMDGPUISelDAGToDAG.cpp1050 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32); in SelectADDRIndirect()
1054 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32); in SelectADDRIndirect()
3170 case 2: RegClassID = R600::R600_Reg64RegClassID; break; in Select()
3173 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
3175 RegClassID = R600::R600_Reg128RegClassID; in Select()
3193 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32); in SelectADDRIndirect()
3197 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32); in SelectADDRIndirect()
3228 R600::ZERO, MVT::i32); in SelectADDRVTX_READ()
DAMDGPUSubtarget.cpp737 Gen(R600), in R600Subtarget()
DAMDGPUInstructions.td287 // XXX - For some reason R600 version is preferring to use unordered
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp99 if (MI.getOpcode() == R600::RETURN || in encodeInstruction()
100 MI.getOpcode() == R600::FETCH_CLAUSE || in encodeInstruction()
101 MI.getOpcode() == R600::ALU_CLAUSE || in encodeInstruction()
102 MI.getOpcode() == R600::BUNDLE || in encodeInstruction()
103 MI.getOpcode() == R600::KILL) { in encodeInstruction()
108 if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) { in encodeInstruction()
141 if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) && in encodeInstruction()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/TargetInfo/
DAMDGPUTargetInfo.cpp32 RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600", in LLVMInitializeAMDGPUTargetInfo() local
/freebsd-12-stable/contrib/llvm-project/clang/include/clang/Basic/
DBuiltinsAMDGPU.def239 // R600-NI only builtins.

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