Lines Matching refs:R600
31 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
32 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
260 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
276 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
282 MI.getOpcode() == R600::LDS_CMPST_RET) in EmitInstrWithCustomInserter()
286 TII->get(R600::getLDSNoRetOp(MI.getOpcode()))); in EmitInstrWithCustomInserter()
295 case R600::FABS_R600: { in EmitInstrWithCustomInserter()
297 *BB, I, R600::MOV, MI.getOperand(0).getReg(), in EmitInstrWithCustomInserter()
303 case R600::FNEG_R600: { in EmitInstrWithCustomInserter()
305 *BB, I, R600::MOV, MI.getOperand(0).getReg(), in EmitInstrWithCustomInserter()
311 case R600::MASK_WRITE: { in EmitInstrWithCustomInserter()
319 case R600::MOV_IMM_F32: in EmitInstrWithCustomInserter()
327 case R600::MOV_IMM_I32: in EmitInstrWithCustomInserter()
332 case R600::MOV_IMM_GLOBAL_ADDR: { in EmitInstrWithCustomInserter()
335 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X); in EmitInstrWithCustomInserter()
336 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); in EmitInstrWithCustomInserter()
342 case R600::CONST_COPY: { in EmitInstrWithCustomInserter()
344 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST); in EmitInstrWithCustomInserter()
345 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, in EmitInstrWithCustomInserter()
350 case R600::RAT_WRITE_CACHELESS_32_eg: in EmitInstrWithCustomInserter()
351 case R600::RAT_WRITE_CACHELESS_64_eg: in EmitInstrWithCustomInserter()
352 case R600::RAT_WRITE_CACHELESS_128_eg: in EmitInstrWithCustomInserter()
359 case R600::RAT_STORE_TYPED_eg: in EmitInstrWithCustomInserter()
367 case R600::BRANCH: in EmitInstrWithCustomInserter()
368 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP)) in EmitInstrWithCustomInserter()
372 case R600::BRANCH_COND_f32: { in EmitInstrWithCustomInserter()
374 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X), in EmitInstrWithCustomInserter()
375 R600::PREDICATE_BIT) in EmitInstrWithCustomInserter()
377 .addImm(R600::PRED_SETNE) in EmitInstrWithCustomInserter()
380 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND)) in EmitInstrWithCustomInserter()
382 .addReg(R600::PREDICATE_BIT, RegState::Kill); in EmitInstrWithCustomInserter()
386 case R600::BRANCH_COND_i32: { in EmitInstrWithCustomInserter()
388 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X), in EmitInstrWithCustomInserter()
389 R600::PREDICATE_BIT) in EmitInstrWithCustomInserter()
391 .addImm(R600::PRED_SETNE_INT) in EmitInstrWithCustomInserter()
394 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND)) in EmitInstrWithCustomInserter()
396 .addReg(R600::PREDICATE_BIT, RegState::Kill); in EmitInstrWithCustomInserter()
400 case R600::EG_ExportSwz: in EmitInstrWithCustomInserter()
401 case R600::R600_ExportSwz: { in EmitInstrWithCustomInserter()
408 if (NextExportInst->getOpcode() == R600::EG_ExportSwz || in EmitInstrWithCustomInserter()
409 NextExportInst->getOpcode() == R600::R600_ExportSwz) { in EmitInstrWithCustomInserter()
421 unsigned CfInst = (MI.getOpcode() == R600::EG_ExportSwz) ? 84 : 40; in EmitInstrWithCustomInserter()
434 case R600::RETURN: { in EmitInstrWithCustomInserter()
591 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass, in LowerOperation()
592 R600::T1_X, VT); in LowerOperation()
595 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass, in LowerOperation()
596 R600::T1_Y, VT); in LowerOperation()
599 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass, in LowerOperation()
600 R600::T1_Z, VT); in LowerOperation()
603 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass, in LowerOperation()
604 R600::T0_X, VT); in LowerOperation()
607 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass, in LowerOperation()
608 R600::T0_Y, VT); in LowerOperation()
611 return CreateLiveInRegisterRaw(DAG, &R600::R600_TReg32RegClass, in LowerOperation()
612 R600::T0_Z, VT); in LowerOperation()
1516 Register Reg = MF.addLiveIn(VA.getLocReg(), &R600::R600_Reg128RegClass); in LowerFormalArguments()
1989 case R600::FNEG_R600: in FoldOperand()
1995 case R600::FABS_R600: in FoldOperand()
2001 case R600::CONST_COPY: { in FoldOperand()
2003 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in FoldOperand()
2014 TII->getOperandIdx(Opcode, R600::OpName::src0), in FoldOperand()
2015 TII->getOperandIdx(Opcode, R600::OpName::src1), in FoldOperand()
2016 TII->getOperandIdx(Opcode, R600::OpName::src2), in FoldOperand()
2017 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in FoldOperand()
2018 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in FoldOperand()
2019 TII->getOperandIdx(Opcode, R600::OpName::src0_Z), in FoldOperand()
2020 TII->getOperandIdx(Opcode, R600::OpName::src0_W), in FoldOperand()
2021 TII->getOperandIdx(Opcode, R600::OpName::src1_X), in FoldOperand()
2022 TII->getOperandIdx(Opcode, R600::OpName::src1_Y), in FoldOperand()
2023 TII->getOperandIdx(Opcode, R600::OpName::src1_Z), in FoldOperand()
2024 TII->getOperandIdx(Opcode, R600::OpName::src1_W) in FoldOperand()
2037 if (Reg->getReg() == R600::ALU_CONST) { in FoldOperand()
2052 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32); in FoldOperand()
2055 case R600::MOV_IMM_GLOBAL_ADDR: in FoldOperand()
2060 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32); in FoldOperand()
2062 case R600::MOV_IMM_I32: in FoldOperand()
2063 case R600::MOV_IMM_F32: { in FoldOperand()
2064 unsigned ImmReg = R600::ALU_LITERAL_X; in FoldOperand()
2067 if (Src.getMachineOpcode() == R600::MOV_IMM_F32) { in FoldOperand()
2071 ImmReg = R600::ZERO; in FoldOperand()
2073 ImmReg = R600::HALF; in FoldOperand()
2075 ImmReg = R600::ONE; in FoldOperand()
2083 ImmReg = R600::ZERO; in FoldOperand()
2085 ImmReg = R600::ONE_INT; in FoldOperand()
2094 if (ImmReg == R600::ALU_LITERAL_X) { in FoldOperand()
2122 if (Opcode == R600::DOT_4) { in PostISelFolding()
2124 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in PostISelFolding()
2125 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in PostISelFolding()
2126 TII->getOperandIdx(Opcode, R600::OpName::src0_Z), in PostISelFolding()
2127 TII->getOperandIdx(Opcode, R600::OpName::src0_W), in PostISelFolding()
2128 TII->getOperandIdx(Opcode, R600::OpName::src1_X), in PostISelFolding()
2129 TII->getOperandIdx(Opcode, R600::OpName::src1_Y), in PostISelFolding()
2130 TII->getOperandIdx(Opcode, R600::OpName::src1_Z), in PostISelFolding()
2131 TII->getOperandIdx(Opcode, R600::OpName::src1_W) in PostISelFolding()
2134 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_X), in PostISelFolding()
2135 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Y), in PostISelFolding()
2136 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_Z), in PostISelFolding()
2137 TII->getOperandIdx(Opcode, R600::OpName::src0_neg_W), in PostISelFolding()
2138 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_X), in PostISelFolding()
2139 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Y), in PostISelFolding()
2140 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_Z), in PostISelFolding()
2141 TII->getOperandIdx(Opcode, R600::OpName::src1_neg_W) in PostISelFolding()
2144 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_X), in PostISelFolding()
2145 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Y), in PostISelFolding()
2146 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_Z), in PostISelFolding()
2147 TII->getOperandIdx(Opcode, R600::OpName::src0_abs_W), in PostISelFolding()
2148 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_X), in PostISelFolding()
2149 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Y), in PostISelFolding()
2150 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_Z), in PostISelFolding()
2151 TII->getOperandIdx(Opcode, R600::OpName::src1_abs_W) in PostISelFolding()
2159 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in PostISelFolding()
2167 } else if (Opcode == R600::REG_SEQUENCE) { in PostISelFolding()
2177 TII->getOperandIdx(Opcode, R600::OpName::src0), in PostISelFolding()
2178 TII->getOperandIdx(Opcode, R600::OpName::src1), in PostISelFolding()
2179 TII->getOperandIdx(Opcode, R600::OpName::src2) in PostISelFolding()
2182 TII->getOperandIdx(Opcode, R600::OpName::src0_neg), in PostISelFolding()
2183 TII->getOperandIdx(Opcode, R600::OpName::src1_neg), in PostISelFolding()
2184 TII->getOperandIdx(Opcode, R600::OpName::src2_neg) in PostISelFolding()
2187 TII->getOperandIdx(Opcode, R600::OpName::src0_abs), in PostISelFolding()
2188 TII->getOperandIdx(Opcode, R600::OpName::src1_abs), in PostISelFolding()
2198 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in PostISelFolding()
2200 int ImmIdx = TII->getOperandIdx(Opcode, R600::OpName::literal); in PostISelFolding()