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Searched refs:vdst (Results 1 – 23 of 23) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDVOP1Instructions.td14 bits<8> vdst;
19 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
24 bits<8> vdst;
28 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
33 bits<8> vdst;
37 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
92 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
96 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
98 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
130 let Asm64 = "$vdst, $src0$clamp$omod";
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HDVOP2Instructions.td14 bits<8> vdst;
20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
26 bits<8> vdst;
33 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
40 bits<8> vdst;
45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
51 bits<8> vdst;
56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
113 [(set P.DstVT:$vdst,
119 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
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HDVOP3Instructions.td18 list<dag> ret3 = [(set P.DstVT:$vdst,
23 list<dag> ret2 = [(set P.DstVT:$vdst,
27 list<dag> ret1 = [(set P.DstVT:$vdst,
36 list<dag> ret3 = [(set P.DstVT:$vdst,
42 list<dag> ret2 = [(set P.DstVT:$vdst,
47 list<dag> ret1 = [(set P.DstVT:$vdst,
56 list<dag> ret3 = [(set P.DstVT:$vdst,
62 list<dag> ret2 = [(set P.DstVT:$vdst,
67 list<dag> ret1 = [(set P.DstVT:$vdst,
76 list<dag> ret3 = [(set P.DstVT:$vdst,
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HDSIPeepholeSDWA.cpp388 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToSDWA()
404 AMDGPU::OpName::vdst); in convertToSDWA()
470 MachineOperand *Operand = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToSDWA()
511 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
572 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
610 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
674 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
703 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
836 MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand()
928 NewMI.add(*TII->getNamedOperand(MI, AMDGPU::OpName::vdst)); in pseudoOpConvertToVOP2()
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HDSIInstructions.td43 (outs VINTRPDst:$vdst),
45 "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
46 [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
56 let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
60 } // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
62 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
66 (outs VINTRPDst:$vdst),
68 "v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
69 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
72 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
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HDVOPInstructions.td209 bits<8> vdst;
210 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
214 bits<8> vdst;
215 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
219 bits<8> vdst;
220 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
272 bits<8> vdst;
282 let Inst{7-0} = vdst;
295 bits<8> vdst;
305 let Inst{7-0} = vdst;
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HDDSInstructions.td70 bits<8> vdst;
158 (outs rc:$vdst),
160 "$vdst, $addr, $data0$offset$gds"> {
182 (outs rc:$vdst),
184 "$vdst, $addr, $data0, $data1$offset$gds"> {
206 (outs rc:$vdst),
208 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
229 (outs rc:$vdst),
233 "$vdst, $addr$offset$gds"> {
234 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
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HDFLATInstructions.td89 bits<8> vdst;
125 let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
140 (outs regClass:$vdst),
147 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
155 let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
198 (outs regClass:$vdst),
202 …" $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$sl…
285 (outs vdst_rc:$vdst),
287 " $vdst, $vaddr, $vdata$offset glc$slc",
288 [(set vt:$vdst,
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HDMIMGInstructions.td405 : MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
406 let Constraints = "$vdst = $vdata";
412 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da";
432 : MIMG_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst),
434 let Constraints = "$vdst = $vdata";
440 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe";
446 : MIMG_nsa_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), num_addrs,
448 let Constraints = "$vdst = $vdata";
HDGCNDPPCombine.cpp174 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
357 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in combineDPPMov()
HDSIFixupVectorISel.cpp183 bool HasVdst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst) != nullptr; in fixupGlobalSaddr()
HDSIInstrFormats.td251 bits<8> vdst;
260 let Inst{25-18} = vdst;
HDSIInstrInfo.td1866 (outs DstRCExt:$vdst)),
1875 (outs DstRCSDWA:$vdst)),
1883 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1897 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1914 string dst = " $vdst";
1934 string dst = " $vdst";
1961 "$vdst"),
1981 "$vdst"),
1997 "$vdst"),
2026 "$vdst"), // VOP1/2
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HDVOP3PInstructions.td37 let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", "");
40 " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
353 let Asm64 = " $vdst, $src0, $src1, $src2$cbsz$abid$blgp";
HDSIInstrInfo.cpp457 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst); in shouldClusterMemOps()
460 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst); in shouldClusterMemOps()
465 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst); in shouldClusterMemOps()
466 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst); in shouldClusterMemOps()
2651 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst); in convertToThreeAddress()
3075 int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst); in buildShrunkInst()
3316 int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in verifyInstruction()
3597 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst); in verifyInstruction()
HDSILoadStoreOptimizer.cpp960 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
961 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
HDGCNHazardRecognizer.cpp957 SDSTName = AMDGPU::OpName::vdst; in fixSMEMtoVectorWriteHazards()
/freebsd-11-stable/sys/sparc64/sparc64/
HDpmap.c1879 vm_offset_t vdst; in pmap_copy_page() local
1896 vdst = TLB_PHYS_TO_DIRECT(pdst); in pmap_copy_page()
1898 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE); in pmap_copy_page()
1905 vdst = TLB_PHYS_TO_DIRECT(pdst); in pmap_copy_page()
1906 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst, in pmap_copy_page()
1911 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE); in pmap_copy_page()
1912 tp = tsb_kvtotte(vdst); in pmap_copy_page()
1915 tp->tte_vpn = TV_VPN(vdst, TS_8K); in pmap_copy_page()
1916 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst, in pmap_copy_page()
1918 tlb_page_demap(kernel_pmap, vdst); in pmap_copy_page()
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/freebsd-11-stable/contrib/tcsh/
HDtc.os.c980 xmemmove(void *vdst, const void *vsrc, size_t len) in xmemmove() argument
983 char *dst = vdst; in xmemmove()
986 return vdst; in xmemmove()
998 return vdst; in xmemmove()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
HDAMDGPUDisassembler.cpp466 AMDGPU::OpName::vdst); in convertMIMGInst()
/freebsd-11-stable/sys/dev/isp/
HDisp.c2242 isp_icb_2400_vpinfo_t vpinfo, *vdst; in isp_fibre_init_2400() local
2258 vdst = (isp_icb_2400_vpinfo_t *) off; in isp_fibre_init_2400()
2259 isp_put_icb_2400_vpinfo(isp, &vpinfo, vdst); in isp_fibre_init_2400()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsicsAMDGPU.td1727 // llvm.amdgcn.mfma.f32.* vdst, srcA, srcB, srcC, cbsz, abid, blgp
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
HDAMDGPUAsmParser.cpp2894 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in validateEarlyClobberLimitations()