Lines Matching refs:vdst

18   list<dag> ret3 = [(set P.DstVT:$vdst,
23   list<dag> ret2 = [(set P.DstVT:$vdst,
27   list<dag> ret1 = [(set P.DstVT:$vdst,
36   list<dag> ret3 = [(set P.DstVT:$vdst,
42   list<dag> ret2 = [(set P.DstVT:$vdst,
47   list<dag> ret1 = [(set P.DstVT:$vdst,
56   list<dag> ret3 = [(set P.DstVT:$vdst,
62   list<dag> ret2 = [(set P.DstVT:$vdst,
67   list<dag> ret1 = [(set P.DstVT:$vdst,
76   list<dag> ret3 = [(set P.DstVT:$vdst,
82   list<dag> ret2 = [(set P.DstVT:$vdst,
87   list<dag> ret1 = [(set P.DstVT:$vdst,
96 …list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$sr…
97 …list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$sr…
98   list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))];
105 …list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$cl…
106   list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
107   list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
114   list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2,
144 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
146   let Outs64 = (outs DstRC.RegClass:$vdst);
149   let Outs64 = (outs DstRC.RegClass:$vdst);
176   let Outs64 = (outs DstRC.RegClass:$vdst);
196   let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
197   let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
216   let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
217   let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
234   let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
242   let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
251     " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
278   let Outs64 = (outs VGPR_32:$vdst);
379 let Constraints = "@earlyclobber $vdst" in {
381 } // End Constraints = "@earlyclobber $vdst"
411 let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
414 } // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
458        [(set f16:$vdst,
483        [(set f32:$vdst, (AMDGPUinterp_p1ll_f16 f32:$src0, (i32 timm:$attrchan),
490        [(set f32:$vdst, (AMDGPUinterp_p1lv_f16 f32:$src0, (i32 timm:$attrchan),
641   let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
644   } // End $vdst = $vdst_in, DisableEncoding $vdst_in