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Searched refs:v4f32 (Results 1 – 25 of 83) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCInstrQPX.td77 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4f32;
82 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32;
87 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32;
120 [(set v4f32:$FRT, (fadd v4f32:$FRA, v4f32:$FRB))]>;
131 [(set v4f32:$FRT, (fsub v4f32:$FRA, v4f32:$FRB))]>;
141 [(set v4f32:$FRT, (PPCfre v4f32:$FRB))]>;
150 [(set v4f32:$FRT, (PPCfrsqrte v4f32:$FRB))]>;
163 [(set v4f32:$FRT, (fmul v4f32:$FRA, v4f32:$FRC))]>;
178 [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>;
189 [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
[all …]
HDPPCInstrAltivec.td321 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
464 [(set v4f32:$vD,
465 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
470 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
471 (fneg v4f32:$vB))))]>;
493 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
525 [(set v4f32:$vD,
529 [(set v4f32:$vD,
534 (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>;
538 (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>;
[all …]
HDPPCInstrVSX.td58 SDTCisVT<0, v4f32>, SDTCisPtrTy<1>
62 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2>
236 [(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
246 [(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
262 [(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
350 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
382 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
414 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
446 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
490 [(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
[all …]
HDPPCCallingConv.td64 CCIfType<[v4f64, v4f32, v4i1],
67 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
102 CCIfType<[v4f64, v4f32, v4i1],
107 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
161 CCIfType<[v4f64, v4f32, v4i1],
163 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
230 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,
247 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
251 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
HDREADME_P9.txt414 - Not useful for extraction of f32 from v4f32 (the current pattern is better -
431 (set v4f32:$XT, (int_ppc_vsx_xviexpsp v4f32:$XA, v4f32:$XB))
436 (set v4f32:$XT, (int_ppc_vsx_xvxexpsp v4f32:$XB))
438 (set v4f32:$XT, (int_ppc_vsx_xvxsigsp v4f32:$XB))
451 (set v4f32:$XT, (int_ppc_vsx_xvtstdcsp v4f32:$XB, i7:$DCMX))
HDPPCISelLowering.cpp731 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
732 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
733 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
734 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
749 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
754 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
755 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
758 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
759 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
770 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyInstrSIMD.td27 defm "" : ARGUMENT<V128, v4f32>;
51 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
82 ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
149 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
207 defm "" : ConstVec<v4f32,
252 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
312 defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
325 def : ScalarSplatPat<v4f32, f32, F32>;
378 defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
405 def : Pat<(vector_extract (v4f32 V128:$vec), undef),
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp327 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
330 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
342 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
343 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
344 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
345 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
368 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
371 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
383 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
384 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
[all …]
HDAArch64CallingConvention.td32 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
38 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
112 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
120 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
128 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
137 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
154 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
189 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
229 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
244 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
[all …]
HDAArch64ISelDAGToDAG.cpp1842 (VT != MVT::v4f32 || NarrowVT != MVT::v4f16)) in tryHighFPExt()
3197 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3224 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3251 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3278 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3305 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3332 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3359 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3386 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3413 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
[all …]
HDAArch64InstrInfo.td815 foreach Ty = [v4f32, v2f64] in {
2102 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
2150 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
2293 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2480 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2812 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
2840 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>;
2912 def : Pat<(store (v4f32 FPR128:$Rt),
2962 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>;
3048 def : Pat<(store (v4f32 FPR128:$Rt),
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86InstrFMA.td126 loadv4f32, loadv8f32, X86any_Fmadd, v4f32, v8f32,
129 loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32,
132 loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32,
135 loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32,
157 loadv8f32, X86Fnmadd, v4f32, v8f32, SchedWriteFMA>;
159 loadv8f32, X86Fnmsub, v4f32, v8f32, SchedWriteFMA>;
375 defm : scalar_fma_patterns<X86any_Fmadd, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
376 defm : scalar_fma_patterns<X86Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
377 defm : scalar_fma_patterns<X86Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
378 defm : scalar_fma_patterns<X86Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
[all …]
HDX86TargetTransformInfo.cpp187 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps in getArithmeticInstrCost()
205 { ISD::FDIV, MVT::v4f32, 39 }, // divps in getArithmeticInstrCost()
703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
740 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getArithmeticInstrCost()
755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
765 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
768 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
833 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
HDX86InstrSSE.td135 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
268 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
274 defm MOVSS : sse12_move_rm<FR32, v4f32, f32mem, loadf32, X86vzload32, "movss",
282 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
298 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
299 (VMOVSSrr (v4f32 (V_SET0)), VR128:$src)>;
306 (v4f32 (VMOVSSrr (v4f32 (V_SET0)),
307 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>;
317 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
318 (MOVSSrr (v4f32 (V_SET0)), VR128:$src)>;
[all …]
HDX86InstrVecCompiler.td20 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
21 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
28 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
29 (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X)>;
36 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
45 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)),
72 defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
83 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
116 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>;
125 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>;
[all …]
HDX86InstrFragmentsSIMD.td97 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
98 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
405 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
406 SDTCisVT<1, v4f32>,
407 SDTCisVT<2, v4f32>]>>;
410 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
411 SDTCisVT<1, v4f32>,
412 SDTCisVT<2, v4f32>]>>;
414 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
415 SDTCisVT<1, v4f32>,
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp163 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
244 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
254 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
255 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
256 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
257 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
267 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
[all …]
HDARMInstrMVE.td347 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, 0b01, "f", ?>;
348 def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, 0b10, "f", ?>;
1091 def : Pat<(v4f32 (fmaxnum (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
1092 (v4f32 (MVE_VMAXNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
1095 def : Pat<(v4f32 (int_arm_mve_max_predicated (v4f32 MQPR:$val1), (v4f32 MQPR:$val2), (i32 0),
1096 (v4i1 VCCR:$mask), (v4f32 MQPR:$inactive))),
1097 (v4f32 (MVE_VMAXNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2),
1099 (v4f32 MQPR:$inactive)))>;
1111 def : Pat<(v4f32 (fminnum (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
1112 (v4f32 (MVE_VMINNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
[all …]
HDARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
186 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
212 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
234 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
HDARMInstrNEON.td1090 def : Pat<(vector_insert (v4f32 QPR:$src),
1101 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1412 def : Pat<(v4f32 (ARMvdup (f32 (load addrmode6dup:$addr)))),
2148 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
3358 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3361 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
4258 v4f32, v4f32, fadd, 1>;
4321 v4f32, v4f32, fmul, 1>;
4330 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4351 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZCallingConv.td56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
76 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
120 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
127 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
132 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
HDSystemZInstrVector.td133 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
201 defm : ReplicatePeephole<VLREPF, v4f32, load, f32>;
223 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
268 def : Pat<(v4f32 (z_loadeswap bdxaddr12only:$addr)),
309 def : Pat<(z_storeeswap (v4f32 VR128:$val), bdxaddr12only:$addr),
337 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>;
346 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>;
365 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16_timm:$index)),
458 defm : GenericVectorOps<v4f32, v4i32>;
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsicsNVVM.td1320 "llvm.nvvm.tex.1d.v4f32.s32">;
1324 "llvm.nvvm.tex.1d.v4f32.f32">;
1328 "llvm.nvvm.tex.1d.level.v4f32.f32">;
1333 "llvm.nvvm.tex.1d.grad.v4f32.f32">;
1372 "llvm.nvvm.tex.1d.array.v4f32.s32">;
1376 "llvm.nvvm.tex.1d.array.v4f32.f32">;
1381 "llvm.nvvm.tex.1d.array.level.v4f32.f32">;
1386 "llvm.nvvm.tex.1d.array.grad.v4f32.f32">;
1427 "llvm.nvvm.tex.2d.v4f32.s32">;
1431 "llvm.nvvm.tex.2d.v4f32.f32">;
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDR600Instructions.td420 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
511 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
522 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
527 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
532 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
537 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
1093 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))],
1708 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;
1719 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>;
1750 def : Extract_Element <f32, v4f32, 0, sub0>;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsMSAInstrInfo.td114 def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
116 def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
118 def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
120 def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
124 def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
126 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
130 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
132 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
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