Lines Matching refs:v4f32
347 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, 0b01, "f", ?>;
348 def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, 0b10, "f", ?>;
1091 def : Pat<(v4f32 (fmaxnum (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
1092 (v4f32 (MVE_VMAXNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
1095 def : Pat<(v4f32 (int_arm_mve_max_predicated (v4f32 MQPR:$val1), (v4f32 MQPR:$val2), (i32 0),
1096 (v4i1 VCCR:$mask), (v4f32 MQPR:$inactive))),
1097 (v4f32 (MVE_VMAXNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2),
1099 (v4f32 MQPR:$inactive)))>;
1111 def : Pat<(v4f32 (fminnum (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
1112 (v4f32 (MVE_VMINNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
1115 def : Pat<(v4f32 (int_arm_mve_min_predicated (v4f32 MQPR:$val1), (v4f32 MQPR:$val2),
1116 (i32 0), (v4i1 VCCR:$mask), (v4f32 MQPR:$inactive))),
1117 (v4f32 (MVE_VMINNMf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2),
1119 (v4f32 MQPR:$inactive)))>;
1263 def : Pat<(v4f32 (ARMvrev64 (v4f32 MQPR:$src))),
1264 (v4f32 (MVE_VREV64_32 (v4f32 MQPR:$src)))>;
1573 def : Pat<(extractelt (v4f32 MQPR:$src), imm:$lane),
1575 def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
1576 …(INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane)…
1587 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1588 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
1589 def : Pat<(v4f32 (scalar_to_vector GPR:$src)),
1590 (MVE_VMOV_to_lane_32 (v4f32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
2040 def : Pat<(v4f32 (ARMvdup (f32 SPR:$elem))),
2041 (v4f32 (MVE_VDUP32 (i32 (COPY_TO_REGCLASS (f32 SPR:$elem), rGPR))))>;
2045 def : Pat<(v4f32 (ARMvduplane (v4f32 MQPR:$src), imm:$lane)),
2266 def : Pat<(v4f32 (ARMvmovFPImm timm:$simm)),
2267 (v4f32 (MVE_VMOVimmf32 nImmVMOVF32:$simm))>;
3147 def : Pat<(v4f32 (frint (v4f32 MQPR:$val1))),
3148 (v4f32 (MVE_VRINTf32X (v4f32 MQPR:$val1)))>;
3151 def : Pat<(v4f32 (fround (v4f32 MQPR:$val1))),
3152 (v4f32 (MVE_VRINTf32A (v4f32 MQPR:$val1)))>;
3155 def : Pat<(v4f32 (ftrunc (v4f32 MQPR:$val1))),
3156 (v4f32 (MVE_VRINTf32Z (v4f32 MQPR:$val1)))>;
3159 def : Pat<(v4f32 (ffloor (v4f32 MQPR:$val1))),
3160 (v4f32 (MVE_VRINTf32M (v4f32 MQPR:$val1)))>;
3163 def : Pat<(v4f32 (fceil (v4f32 MQPR:$val1))),
3164 (v4f32 (MVE_VRINTf32P (v4f32 MQPR:$val1)))>;
3299 def : Pat<(v4f32 (fma (v4f32 MQPR:$src1), (v4f32 MQPR:$src2), (v4f32 MQPR:$src3))),
3300 (v4f32 (MVE_VFMAf32 $src3, $src1, $src2))>;
3303 def : Pat<(v4f32 (fma (fneg (v4f32 MQPR:$src1)), (v4f32 MQPR:$src2), (v4f32 MQPR:$src3))),
3304 (v4f32 (MVE_VFMSf32 $src3, $src1, $src2))>;
3548 def : Pat<(v4i32 (fp_to_sint (v4f32 MQPR:$src))),
3549 (v4i32 (MVE_VCVTs32f32z (v4f32 MQPR:$src)))>;
3550 def : Pat<(v4i32 (fp_to_uint (v4f32 MQPR:$src))),
3551 (v4i32 (MVE_VCVTu32f32z (v4f32 MQPR:$src)))>;
3556 def : Pat<(v4f32 (sint_to_fp (v4i32 MQPR:$src))),
3557 (v4f32 (MVE_VCVTf32s32n (v4i32 MQPR:$src)))>;
3558 def : Pat<(v4f32 (uint_to_fp (v4i32 MQPR:$src))),
3559 (v4f32 (MVE_VCVTf32u32n (v4i32 MQPR:$src)))>;
3591 def : Pat<(v4f32 (fabs MQPR:$src)),
3601 def : Pat<(v4f32 (fneg MQPR:$src)),
3824 def f32 : Pat<(v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)),
3825 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
3829 def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))),
3830 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
3836 def f32 : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)),
3837 (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc))>;
3841 def f32r : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup SPR:$v2)), fc)),
3842 … (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 (COPY_TO_REGCLASS (f32 SPR:$v2), rGPR)), fc))>;
3846 def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)))),
3847 (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
3851 …def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup SPR:$v2)), …
3852 …(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 (COPY_TO_REGCLASS (f32 SPR:$v2), rGPR)), fc, ARMVCCThen…
4246 (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))),
4247 (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
4249 (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half),
4251 (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm),
5028 defm : MVE_vst24_patterns<32, v4f32>;
5711 def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
5712 (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>;
5727 def : Pat<(v4f32 (vselect (v4i32 MQPR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
5728 (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
5764 def : Pat<(v4f32 (uint_to_fp (v4i1 VCCR:$pred))),
5765 …(v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 112)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred…
5770 def : Pat<(v4f32 (sint_to_fp (v4i1 VCCR:$pred))),
5771 …(v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 240)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred…
5776 def : Pat<(v4i1 (fp_to_uint (v4f32 MQPR:$v1))),
5777 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
5780 def : Pat<(v4i1 (fp_to_sint (v4f32 MQPR:$v1))),
5781 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
6095 def : MVE_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>;
6116 def : MVE_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>;
6137 def : MVE_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>;
6169 def : MVE_vector_store_typed<v4f32, MVE_VSTRWU32, alignedstore32, 2>;
6176 def : MVE_vector_load_typed<v4f32, MVE_VLDRWU32, alignedload32, 2>;
6185 def : Pat<(v4f32 (load t2addrmode_imm7<0>:$addr)),
6186 (v4f32 (MVE_VREV32_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
6197 def : Pat<(store (v4f32 MQPR:$val), t2addrmode_imm7<0>:$addr),
6213 def : MVE_vector_offset_store_typed<v4f32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
6214 def : MVE_vector_offset_store_typed<v4f32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
6223 def : MVE_vector_maskedstore_typed<v4f32, MVE_VSTRWU32, aligned_maskedstvi32, 2>;
6234 …def : MVE_vector_offset_maskedstore_typed<v4f32, MVE_VSTRWU32_pre, aligned_pre_maskedstorevi32, 2>;
6235 …def : MVE_vector_offset_maskedstore_typed<v4f32, MVE_VSTRWU32_post, aligned_post_maskedstorevi32, …
6242 def : MVE_vector_maskedload_typed<v4f32, MVE_VLDRWU32, aligned_maskedloadvi32, 2>;
6295 def : Pat<(v4i32 (bitconvert (v4f32 MQPR:$src))), (v4i32 MQPR:$src)>;
6296 def : Pat<(v4f32 (bitconvert (v4i32 MQPR:$src))), (v4f32 MQPR:$src)>;
6303 def : Pat<(v2f64 (bitconvert (v4f32 MQPR:$src))), (v2f64 MQPR:$src)>;
6309 def : Pat<(v2i64 (bitconvert (v4f32 MQPR:$src))), (v2i64 MQPR:$src)>;
6315 def : Pat<(v4f32 (bitconvert (v2f64 MQPR:$src))), (v4f32 MQPR:$src)>;
6316 def : Pat<(v4f32 (bitconvert (v2i64 MQPR:$src))), (v4f32 MQPR:$src)>;
6317 def : Pat<(v4f32 (bitconvert (v8f16 MQPR:$src))), (v4f32 MQPR:$src)>;
6318 def : Pat<(v4f32 (bitconvert (v8i16 MQPR:$src))), (v4f32 MQPR:$src)>;
6319 def : Pat<(v4f32 (bitconvert (v16i8 MQPR:$src))), (v4f32 MQPR:$src)>;
6329 def : Pat<(v8f16 (bitconvert (v4f32 MQPR:$src))), (v8f16 MQPR:$src)>;
6335 def : Pat<(v8i16 (bitconvert (v4f32 MQPR:$src))), (v8i16 MQPR:$src)>;
6341 def : Pat<(v16i8 (bitconvert (v4f32 MQPR:$src))), (v16i8 MQPR:$src)>;
6348 def : Pat<(v2f64 (bitconvert (v4f32 MQPR:$src))), (v2f64 (MVE_VREV64_32 MQPR:$src))>;
6354 def : Pat<(v2i64 (bitconvert (v4f32 MQPR:$src))), (v2i64 (MVE_VREV64_32 MQPR:$src))>;
6360 def : Pat<(v4f32 (bitconvert (v2f64 MQPR:$src))), (v4f32 (MVE_VREV64_32 MQPR:$src))>;
6361 def : Pat<(v4f32 (bitconvert (v2i64 MQPR:$src))), (v4f32 (MVE_VREV64_32 MQPR:$src))>;
6362 def : Pat<(v4f32 (bitconvert (v8f16 MQPR:$src))), (v4f32 (MVE_VREV32_16 MQPR:$src))>;
6363 def : Pat<(v4f32 (bitconvert (v8i16 MQPR:$src))), (v4f32 (MVE_VREV32_16 MQPR:$src))>;
6364 def : Pat<(v4f32 (bitconvert (v16i8 MQPR:$src))), (v4f32 (MVE_VREV32_8 MQPR:$src))>;
6374 def : Pat<(v8f16 (bitconvert (v4f32 MQPR:$src))), (v8f16 (MVE_VREV32_16 MQPR:$src))>;
6380 def : Pat<(v8i16 (bitconvert (v4f32 MQPR:$src))), (v8i16 (MVE_VREV32_16 MQPR:$src))>;
6386 def : Pat<(v16i8 (bitconvert (v4f32 MQPR:$src))), (v16i8 (MVE_VREV32_8 MQPR:$src))>;