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Searched refs:reg_val (Results 1 – 25 of 55) sorted by relevance

123

/freebsd-11-stable/sys/dev/liquidio/base/
HDcn23xx_pf_device.c143 uint64_t reg_val; in lio_cn23xx_pf_setup_global_mac_regs() local
151 reg_val = in lio_cn23xx_pf_setup_global_mac_regs()
155 reg_val = pf_num * LIO_CN23XX_PF_MAX_RINGS; in lio_cn23xx_pf_setup_global_mac_regs()
158 reg_val = reg_val | in lio_cn23xx_pf_setup_global_mac_regs()
163 reg_val); in lio_cn23xx_pf_setup_global_mac_regs()
198 volatile uint64_t reg_val = in lio_cn23xx_pf_reset_io_queues() local
201 while ((reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) && in lio_cn23xx_pf_reset_io_queues()
202 !(reg_val & LIO_CN23XX_PKT_INPUT_CTL_QUIET) && in lio_cn23xx_pf_reset_io_queues()
204 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
216 reg_val &= ~LIO_CN23XX_PKT_INPUT_CTL_RST; in lio_cn23xx_pf_reset_io_queues()
[all …]
/freebsd-11-stable/sys/arm/allwinner/
HDif_emac.c313 uint32_t reg_val, rxcount; in emac_rxeof() local
333 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); in emac_rxeof()
334 if (reg_val != EMAC_PACKET_HEADER) { in emac_rxeof()
339 reg_val = EMAC_READ_REG(sc, EMAC_CTL); in emac_rxeof()
340 reg_val &= ~EMAC_CTL_RX_EN; in emac_rxeof()
341 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); in emac_rxeof()
344 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); in emac_rxeof()
345 reg_val |= EMAC_RX_FLUSH_FIFO; in emac_rxeof()
346 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); in emac_rxeof()
361 reg_val = EMAC_READ_REG(sc, EMAC_CTL); in emac_rxeof()
[all …]
/freebsd-11-stable/sys/arm/ti/
HDti_pinmux.c135 uint16_t reg_val; in ti_pinmux_padconf_set_internal() local
138 reg_val = (uint16_t)(state & ti_pinmux_dev.padconf_sate_mask); in ti_pinmux_padconf_set_internal()
155 reg_val |= (uint16_t)(mode & ti_pinmux_dev.padconf_muxmode_mask); in ti_pinmux_padconf_set_internal()
159 reg_val, muxmode); in ti_pinmux_padconf_set_internal()
161 ti_pinmux_write_2(sc, padconf->reg_off, reg_val); in ti_pinmux_padconf_set_internal()
215 uint16_t reg_val; in ti_pinmux_padconf_get() local
226 reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off); in ti_pinmux_padconf_get()
230 *state = (reg_val & ti_pinmux_dev.padconf_sate_mask); in ti_pinmux_padconf_get()
234 *muxmode = padconf->muxmodes[(reg_val & ti_pinmux_dev.padconf_muxmode_mask)]; in ti_pinmux_padconf_get()
257 uint16_t reg_val; in ti_pinmux_padconf_set_gpiomode() local
[all …]
/freebsd-11-stable/sys/dev/qlnx/qlnxe/
HDecore_init_fw_funcs.c661 u32 reg_val, i; in ecore_poll_on_qm_cmd_ready() local
663 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; i++) { in ecore_poll_on_qm_cmd_ready()
665 reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY); in ecore_poll_on_qm_cmd_ready()
1301 u32 reg_val; in ecore_set_vxlan_enable() local
1304 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); in ecore_set_vxlan_enable()
1305 …SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT, vxlan_enable… in ecore_set_vxlan_enable()
1306 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); in ecore_set_vxlan_enable()
1307 if (reg_val) /* TODO: handle E5 init */ in ecore_set_vxlan_enable()
1309 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); in ecore_set_vxlan_enable()
1312 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) in ecore_set_vxlan_enable()
[all …]
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
HDar9300_gpio.c429 u_int32_t reg_val; in ar9300_gpio_set_intr() local
463 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr()
465 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr()
466 OS_REG_WRITE(ah, regs[i], reg_val); in ar9300_gpio_set_intr()
470 field_val = (reg_val >> shifts[i]) & gpio_mask; in ar9300_gpio_set_intr()
477 reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)); in ar9300_gpio_set_intr()
481 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr()
484 reg_val |= (1 << reg_bit); in ar9300_gpio_set_intr()
486 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), reg_val); in ar9300_gpio_set_intr()
490 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr()
[all …]
HDar9300_reset.c3217 u_int32_t reg_val;
3232 reg_val = OS_REG_READ(ah, AR9285_AN_RXTXBB1);
3233 reg_val |= ((0x1 << 5) | (0x1 << 7));
3234 OS_REG_WRITE(ah, AR9285_AN_RXTXBB1, reg_val);
3237 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G7);
3238 reg_val &= 0xfffffffd;
3239 OS_REG_WRITE(ah, AR9285_AN_RF2G7, reg_val);
3242 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1);
3243 reg_val &= 0xfffff7ff;
3244 OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val);
[all …]
HDar9300_recv.c283 u_int32_t reg_val = 0; in ar9300_promisc_mode() local
284 reg_val = OS_REG_READ(ah, AR_RX_FILTER); in ar9300_promisc_mode()
286 reg_val |= AR_RX_PROM; in ar9300_promisc_mode()
288 reg_val &= ~AR_RX_PROM; in ar9300_promisc_mode()
290 OS_REG_WRITE(ah, AR_RX_FILTER, reg_val); in ar9300_promisc_mode()
/freebsd-11-stable/sys/dev/ixgbe/
HDixgbe_x550.c2237 u32 reg_val; in ixgbe_setup_kr_speed_x550em() local
2241 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val); in ixgbe_setup_kr_speed_x550em()
2245 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; in ixgbe_setup_kr_speed_x550em()
2246 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | in ixgbe_setup_kr_speed_x550em()
2251 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; in ixgbe_setup_kr_speed_x550em()
2255 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; in ixgbe_setup_kr_speed_x550em()
2259 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_kr_speed_x550em()
2265 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val); in ixgbe_setup_kr_speed_x550em()
2270 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; in ixgbe_setup_kr_speed_x550em()
2271 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; in ixgbe_setup_kr_speed_x550em()
[all …]
HDixgbe_82599.h63 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
64 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
HDixgbe_vf.c252 u32 reg_val; in ixgbe_stop_adapter_vf() local
273 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i)); in ixgbe_stop_adapter_vf()
274 reg_val &= ~IXGBE_RXDCTL_ENABLE; in ixgbe_stop_adapter_vf()
275 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); in ixgbe_stop_adapter_vf()
/freebsd-11-stable/sys/arm/mv/
HDgpio.c370 uint32_t reg_val; in mv_gpio_reg_set() local
372 reg_val = mv_gpio_reg_read(reg); in mv_gpio_reg_set()
373 reg_val |= GPIO(pin); in mv_gpio_reg_set()
374 mv_gpio_reg_write(reg, reg_val); in mv_gpio_reg_set()
380 uint32_t reg_val; in mv_gpio_reg_clear() local
382 reg_val = mv_gpio_reg_read(reg); in mv_gpio_reg_clear()
383 reg_val &= ~(GPIO(pin)); in mv_gpio_reg_clear()
384 mv_gpio_reg_write(reg, reg_val); in mv_gpio_reg_clear()
507 uint32_t reg, reg_val; in mv_gpio_value_get() local
518 reg_val = mv_gpio_reg_read(reg); in mv_gpio_value_get()
[all …]
/freebsd-11-stable/sys/dev/bxe/
HDecore_init.h747 uint32_t reg_val; in ecore_set_mcp_parity() local
750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
753 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity()
755 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity()
757 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
799 uint32_t reg_val, mcp_aeu_bits = in ecore_clear_blocks_parity() local
815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
817 if (reg_val & reg_mask) in ecore_clear_blocks_parity()
821 reg_val & reg_mask); in ecore_clear_blocks_parity()
826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
[all …]
/freebsd-11-stable/sys/dev/vnic/
HDnicvf_queues.c130 uint64_t reg_val; in nicvf_poll_reg() local
137 reg_val = nicvf_queue_reg_read(nic, reg, qidx); in nicvf_poll_reg()
138 if (((reg_val & bit_mask) >> bit_pos) == val) in nicvf_poll_reg()
2046 uint64_t reg_val; in nicvf_enable_intr() local
2048 reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S); in nicvf_enable_intr()
2052 reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT); in nicvf_enable_intr()
2055 reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT); in nicvf_enable_intr()
2058 reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT); in nicvf_enable_intr()
2061 reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT); in nicvf_enable_intr()
2064 reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT); in nicvf_enable_intr()
[all …]
/freebsd-11-stable/contrib/binutils/gas/config/
HDtc-cr16.c320 return reg->value.reg_val; in get_register()
344 return reg->value.reg_val; in get_register_pair()
359 && ((reg->value.reg_val == 12) || (reg->value.reg_val == 13))) in get_index_register()
360 return reg->value.reg_val; in get_index_register()
375 if ((reg->value.reg_val != 1) || (reg->value.reg_val != 7) in get_index_register_pair()
376 || (reg->value.reg_val != 9) || (reg->value.reg_val > 10)) in get_index_register_pair()
377 return reg->value.reg_val; in get_index_register_pair()
379 as_bad (_("Unknown register pair - index relative mode: `%d'"), reg->value.reg_val); in get_index_register_pair()
2011 unsigned int count = insn->arg[0].constant, reg_val; in warn_if_needed() local
2017 reg_val = getreg_image (insn->arg[1].r); in warn_if_needed()
[all …]
/freebsd-11-stable/contrib/gdb/gdb/
HDfindvar.c261 struct value *reg_val; in value_of_register() local
283 reg_val = allocate_value (register_type (current_gdbarch, regnum)); in value_of_register()
291 raw_buffer, VALUE_CONTENTS_RAW (reg_val)); in value_of_register()
294 memcpy (VALUE_CONTENTS_RAW (reg_val), raw_buffer, in value_of_register()
303 VALUE_LVAL (reg_val) = lval; in value_of_register()
304 VALUE_ADDRESS (reg_val) = addr; in value_of_register()
305 VALUE_REGNO (reg_val) = regnum; in value_of_register()
306 VALUE_OPTIMIZED_OUT (reg_val) = optim; in value_of_register()
307 return reg_val; in value_of_register()
/freebsd-11-stable/sys/dev/mge/
HDif_mge.c458 uint32_t reg_idx, reg_off, reg_val, i; in mge_set_ucast_address() local
463 reg_val = (1 | (queue << 1)) << reg_off; in mge_set_ucast_address()
467 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val); in mge_set_ucast_address()
477 uint32_t reg_val, i; in mge_set_prom_mode() local
485 reg_val = ((1 | (queue << 1)) | (1 | (queue << 1)) << 8 | in mge_set_prom_mode()
489 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), reg_val); in mge_set_prom_mode()
490 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), reg_val); in mge_set_prom_mode()
494 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val); in mge_set_prom_mode()
1091 volatile uint32_t reg_val; in mge_init_locked() local
1146 reg_val = mge_set_port_serial_control(media_status); in mge_init_locked()
[all …]
/freebsd-11-stable/sys/dev/cxgb/common/
HDcxgb_ael1002.c91 struct reg_val { struct
100 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
527 static struct reg_val regs[] = { in ael2005_setup_sr_edc()
824 static struct reg_val regs[] = { in ael2005_setup_twinax_edc()
828 static struct reg_val preemphasis[] = { in ael2005_setup_twinax_edc()
1254 static struct reg_val regs0[] = { in ael2005_reset()
1264 static struct reg_val regs1[] = { in ael2005_reset()
1409 static struct reg_val regs[] = { in ael2020_setup_sr_edc()
1435 static struct reg_val uCclock40MHz[] = { in ael2020_setup_twinax_edc()
1441 static struct reg_val uCclockActivate[] = { in ael2020_setup_twinax_edc()
[all …]
/freebsd-11-stable/contrib/llvm-project/lldb/source/Core/
HDDumpRegisterValue.cpp18 bool lldb_private::DumpRegisterValue(const RegisterValue &reg_val, Stream *s, in DumpRegisterValue() argument
24 if (reg_val.GetData(data)) { in DumpRegisterValue()
/freebsd-11-stable/sys/dev/e1000/
HDe1000_i210.c829 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; in e1000_pll_workaround_i210() local
836 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; in e1000_pll_workaround_i210()
837 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); in e1000_pll_workaround_i210()
865 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); in e1000_pll_workaround_i210()
866 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
874 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); in e1000_pll_workaround_i210()
875 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
/freebsd-11-stable/sys/dev/usb/net/
HDif_smsc.c1358 uint32_t reg_val; in smsc_chip_init() local
1390 if ((err = smsc_read_reg(sc, SMSC_HW_CFG, &reg_val)) != 0) { in smsc_chip_init()
1394 reg_val |= SMSC_HW_CFG_BIR; in smsc_chip_init()
1395 smsc_write_reg(sc, SMSC_HW_CFG, reg_val); in smsc_chip_init()
1423 if ((err = smsc_read_reg(sc, SMSC_HW_CFG, &reg_val)) < 0) { in smsc_chip_init()
1431 reg_val &= ~SMSC_HW_CFG_RXDOFF; in smsc_chip_init()
1432 reg_val |= (ETHER_ALIGN << 9) & SMSC_HW_CFG_RXDOFF; in smsc_chip_init()
1437 reg_val |= (SMSC_HW_CFG_MEF | SMSC_HW_CFG_BCE); in smsc_chip_init()
1439 smsc_write_reg(sc, SMSC_HW_CFG, reg_val); in smsc_chip_init()
1455 reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED | in smsc_chip_init()
[all …]
/freebsd-11-stable/sys/dev/ntb/ntb_hw/
HDntb_hw_intel.c1690 uint64_t reg_val; in xeon_set_sbar_base_and_limit() local
1703 reg_val = intel_ntb_reg_read(4, base_reg); in xeon_set_sbar_base_and_limit()
1704 (void)reg_val; in xeon_set_sbar_base_and_limit()
1707 reg_val = intel_ntb_reg_read(4, lmt_reg); in xeon_set_sbar_base_and_limit()
1708 (void)reg_val; in xeon_set_sbar_base_and_limit()
1711 reg_val = intel_ntb_reg_read(8, base_reg); in xeon_set_sbar_base_and_limit()
1712 (void)reg_val; in xeon_set_sbar_base_and_limit()
1715 reg_val = intel_ntb_reg_read(8, lmt_reg); in xeon_set_sbar_base_and_limit()
1716 (void)reg_val; in xeon_set_sbar_base_and_limit()
2104 uint16_t reg_val; in intel_ntb_poll_link() local
[all …]
/freebsd-11-stable/sys/dev/isci/scil/
HDscic_sds_phy.c253 U32 reg_val = scu_afe_register_read( in scic_sds_phy_link_layer_initialization() local
257 reg_val |= (0x00100000 | (((U32)sas_type) << 19)); in scic_sds_phy_link_layer_initialization()
261 reg_val); in scic_sds_phy_link_layer_initialization()
263 reg_val = scu_afe_register_read( in scic_sds_phy_link_layer_initialization()
267 reg_val |= (((U32)(sas_spread)) << 8); in scic_sds_phy_link_layer_initialization()
271 reg_val); in scic_sds_phy_link_layer_initialization()
279 U32 reg_val = scu_afe_register_read( in scic_sds_phy_link_layer_initialization() local
283 reg_val |= (U32)sata_spread; in scic_sds_phy_link_layer_initialization()
287 reg_val); in scic_sds_phy_link_layer_initialization()
289 reg_val = scu_link_layer_register_read( in scic_sds_phy_link_layer_initialization()
[all …]
/freebsd-11-stable/sys/dev/ixl/
HDi40e_common.c1161 u32 reg_val; in i40e_pre_tx_queue_cfg() local
1168 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
1169 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; in i40e_pre_tx_queue_cfg()
1170 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); in i40e_pre_tx_queue_cfg()
1173 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; in i40e_pre_tx_queue_cfg()
1175 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; in i40e_pre_tx_queue_cfg()
1177 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()
3344 u32 reg_addr, u64 *reg_val, in i40e_aq_debug_read_register() argument
3352 if (reg_val == NULL) in i40e_aq_debug_read_register()
3362 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | in i40e_aq_debug_read_register()
[all …]
HDi40e_prototype.h120 u32 reg_addr, u64 reg_val,
123 u32 reg_addr, u64 *reg_val,
552 u32 reg_addr, u32 *reg_val,
556 u32 reg_addr, u32 reg_val,
558 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
561 u32 reg_addr, u32 reg_val,
565 u32 reg_addr, u32 *reg_val,
/freebsd-11-stable/sys/dev/pms/freebsd/driver/common/
HDlxencrypt.c803 u32 reg_val = 0, new_cipher_mode = 0; in agtiapi_EncryptionIoctl() local
811 reg_val |= TI_ENCRYPT_SEC_MODE_FACT_INIT; in agtiapi_EncryptionIoctl()
815 reg_val |= TI_ENCRYPT_SEC_MODE_A; in agtiapi_EncryptionIoctl()
818 reg_val |= TI_ENCRYPT_SEC_MODE_B; in agtiapi_EncryptionIoctl()
824 reg_val |= TI_ENCRYPT_ATTRIB_CIPHER_XTS; in agtiapi_EncryptionIoctl()
828 printf("%s: Setting security cipher mode to: 0x%08x\n", __FUNCTION__, reg_val); in agtiapi_EncryptionIoctl()
831 rc = tiCOMEncryptSetMode(tiRoot, reg_val); in agtiapi_EncryptionIoctl()

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