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Searched refs:SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (Results 1 – 2 of 2) sorted by relevance

/freebsd-11-stable/sys/arm/nvidia/tegra124/
HDtegra124_car.h225 #define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) macro
HDtegra124_clk_pll.c657 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; in plle_enable()