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Searched refs:HSYNC (Results 1 – 8 of 8) sorted by relevance

/freebsd-11-stable/sys/gnu/dts/arm/
HDam437x-sbc-t43.dts63 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
HDimx53-mba53.dts152 /* VGA_VSYNC, HSYNC with max drive strength */
HDam437x-sk-evm.dts362 AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
HDam43x-epos-evm.dts305 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
HDam437x-gp-evm.dts286 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
HDat91sam9g45.dtsi515 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
/freebsd-11-stable/sys/dev/drm2/i915/
HDintel_display.c3147 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); in ironlake_pch_enable()
3209 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); in lpt_pch_enable()
4660 I915_WRITE(HSYNC(cpu_transcoder), in intel_set_pipe_timings()
6923 int hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_crtc_mode_get()
9522 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_display_capture_error_state()
HDi915_reg.h1581 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) macro