Searched refs:rcr (Results 1 – 5 of 5) sorted by relevance
| /freebsd-10-stable/sys/arm/allwinner/ |
| D | if_emac.c | 199 uint32_t rcr = 0; in emac_set_rx_mode() local
205 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); in emac_set_rx_mode()
208 rcr |= EMAC_RX_UCAD; in emac_set_rx_mode()
209 rcr |= EMAC_RX_DAF; in emac_set_rx_mode()
227 rcr |= EMAC_RX_MCO; in emac_set_rx_mode()
228 rcr |= EMAC_RX_MHF; in emac_set_rx_mode()
233 rcr |= EMAC_RX_BCO; in emac_set_rx_mode()
234 rcr |= EMAC_RX_MCO; in emac_set_rx_mode()
238 rcr |= EMAC_RX_PA; in emac_set_rx_mode()
240 rcr |= EMAC_RX_UCAD; in emac_set_rx_mode()
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 381 "rcr{b}\t$dst", [], IIC_SR>;
383 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
386 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
389 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
391 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
394 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
397 "rcr{l}\t$dst", [], IIC_SR>;
399 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
402 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
405 "rcr{q}\t$dst", [], IIC_SR>;
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| D | X86InstrInfo.td | 2446 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
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| /freebsd-10-stable/sys/dev/ffec/ |
| D | if_ffec.c | 354 uint32_t ecr, rcr, tcr; in ffec_miibus_statchg() local
373 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | in ffec_miibus_statchg()
377 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ in ffec_miibus_statchg()
382 rcr |= FEC_RCR_RMII_MODE; in ffec_miibus_statchg()
385 rcr |= FEC_RCR_RGMII_EN; in ffec_miibus_statchg()
398 rcr |= FEC_RCR_RMII_10T; in ffec_miibus_statchg()
413 rcr |= FEC_RCR_DRT; in ffec_miibus_statchg()
416 rcr |= FEC_RCR_FCE; in ffec_miibus_statchg()
418 WR4(sc, FEC_RCR_REG, rcr); in ffec_miibus_statchg()
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| /freebsd-10-stable/contrib/binutils/opcodes/ |
| D | i386-opc.tbl | 260 rcr, 2, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp1…
261 rcr, 2, 0xc0, 0x3, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|…
262 rcr, 2, 0xd2, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8…
263 rcr, 1, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp…
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