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Searched refs:no_shift (Results 1 – 10 of 10) sorted by relevance

/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp479 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
503 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
619 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
629 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
632 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
637 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
641 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
652 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
655 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
711 ARM_AM::no_shift), in SelectAddrMode2Worker()
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DARMFastISel.cpp2713 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2714 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2715 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2716 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2717 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2718 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2723 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2724 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2725 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2726 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
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DARMSelectionDAGInfo.h25 default: return ARM_AM::no_shift; in getShiftOpcForNode()
DARMLoadStoreOptimizer.cpp1025 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1043 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
DARMFrameLowering.cpp724 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); in emitPopInst()
DARMISelLowering.cpp10582 if (ShOpcVal != ARM_AM::no_shift) { in getARMIndexedAddressParts()
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h28 no_shift = 0, enumerator
DARMMCCodeEmitter.cpp183 case ARM_AM::no_shift: in getShiftOp()
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1006 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1054 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1068 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1093 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1114 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1124 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1852 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
1873 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
2551 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
2713 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()