2713         /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },  in ARMEmitIntExt()
2714         /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },  in ARMEmitIntExt()
2715         /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },  in ARMEmitIntExt()
2716         /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },  in ARMEmitIntExt()
2717         /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },  in ARMEmitIntExt()
2718         /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }  in ARMEmitIntExt()
2723         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2724         /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },  in ARMEmitIntExt()
2725         /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2726         /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },  in ARMEmitIntExt()
2727         /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2728         /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }  in ARMEmitIntExt()
2731         /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2732         /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },  in ARMEmitIntExt()
2733         /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2734         /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },  in ARMEmitIntExt()
2735         /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },  in ARMEmitIntExt()
2736         /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }  in ARMEmitIntExt()
2761   assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&  in ARMEmitIntExt()
2772   bool ImmIsSO = (Shift != ARM_AM::no_shift);  in ARMEmitIntExt()