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Searched refs:f128 (Results 1 – 25 of 34) sorted by relevance

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/freebsd-10-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r199033-sparc.diff72 - [(set f128:$dst, (fextend f32:$src))]>,
75 + [(set f128:$rd, (fextend f32:$rs2))]>,
84 - [(set f128:$dst, (fextend f64:$src))]>,
91 + [(set f128:$rd, (fextend f64:$rs2))]>,
96 - [(set f32:$dst, (fround f128:$src))]>,
99 + [(set f32:$rd, (fround f128:$rs2))]>,
104 - [(set f64:$dst, (fround f128:$src))]>,
107 + [(set f64:$rd, (fround f128:$rs2))]>,
150 - [(set f128:$dst, (fsqrt f128:$src))]>,
153 + [(set f128:$rd, (fsqrt f128:$rs2))]>,
[all …]
Dpatch-r262582-llvm-r202422-sparc.diff22 - if (Op.getValueType() == MVT::f128)
33 if (Op.getValueType() != MVT::f128)
36 - // Lower fabs on f128 to fabs on f64
37 - // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
38 + // Lower fabs/fneg on f128 to fabs/fneg on f64
39 + // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
51 dl, MVT::f128), 0);
Dpatch-r262261-llvm-r198145-sparc.diff55 + assert((LocVT == MVT::f32 || LocVT == MVT::f128
61 + unsigned size = (LocVT == MVT::f128) ? 16 : 8;
62 + unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
71 + else if (LocVT == MVT::f128 && Offset < 16*8)
85 + if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
110 + assert(ValTy == MVT::f128 && "Unexpected type!");
124 + // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
126 + if (!VA.needsCustom() || VA.getValVT() != MVT::f128
133 + if (VA.needsCustom() && VA.getValVT() == MVT::f128
Dpatch-r262261-llvm-r198893-sparc.diff162 - [(set f128:$dst, (load ADDRrr:$addr))]>,
167 - [(set f128:$dst, (load ADDRri:$addr))]>,
171 +defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
223 - [(store f128:$rd, ADDRrr:$addr)]>,
228 - [(store f128:$rd, ADDRri:$addr)]>,
232 +defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
Dpatch-r262261-llvm-r198738-sparc.diff515 + [(set f128:$rd,
516 + (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
530 - [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
532 + [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
542 - [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
544 + [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
Dpatch-r262261-llvm-r198909-sparc.diff107 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
Dpatch-r262261-llvm-r200141-sparc.diff55 setOperationAction(ISD::LOAD, MVT::f128, Legal);
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcInstrInfo.td344 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
365 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
399 defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
410 defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
643 [(set f128:$rd, (fextend f32:$rs2))]>,
652 [(set f128:$rd, (fextend f64:$rs2))]>,
657 [(set f32:$rd, (fround f128:$rs2))]>,
662 [(set f64:$rd, (fround f128:$rs2))]>,
691 [(set f128:$rd, (fsqrt f128:$rs2))]>,
708 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
[all …]
DSparcISelLowering.cpp84 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
103 else if (LocVT == MVT::f128 && Offset < 16*8) in CC_Sparc64_Full()
1013 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1036 assert(ValTy == MVT::f128 && "Unexpected type!"); in fixupVariableFloatArgs()
1119 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1126 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1377 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1390 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in SparcTargetLowering()
[all …]
DSparcISelLowering.h162 return VT != MVT::f128; in ShouldShrinkFPConstant()
DSparcInstr64Bit.td349 [(set f128:$rd,
350 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
DSparcRegisterInfo.td206 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DTargetLoweringBase.cpp415 if (RetVT == MVT::f128) in getFPEXT()
418 if (RetVT == MVT::f128) in getFPEXT()
433 if (OpVT == MVT::f128) in getFPROUND()
440 if (OpVT == MVT::f128) in getFPROUND()
481 } else if (OpVT == MVT::f128) { in getFPTOSINT()
531 } else if (OpVT == MVT::f128) { in getFPTOUINT()
559 if (RetVT == MVT::f128) in getSINTTOFP()
570 if (RetVT == MVT::f128) in getSINTTOFP()
581 if (RetVT == MVT::f128) in getSINTTOFP()
599 if (RetVT == MVT::f128) in getUINTTOFP()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td91 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
312 // f128 multiplication of two FP64 registers.
314 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
315 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
318 // f128 multiplication of an FP64 register and an f64 memory.
320 def : Pat<(fmul (f128 (fextend FP64:$src1)),
321 (f128 (extloadf64 bdxaddr12only:$addr))),
322 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
366 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
DSystemZCallingConv.td37 // is left to higher-level code. Perhaps we could add an f128 definition
52 CCIfType<[f128], CCPassIndirect<i64>>,
DSystemZRegisterInfo.td157 defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q,
DSystemZISelLowering.cpp76 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
246 setOperationAction(ISD::FMA, MVT::f128, Expand); in SystemZTargetLowering()
255 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in SystemZTargetLowering()
256 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in SystemZTargetLowering()
298 case MVT::f128: in isFMAFasterThanFMulAndFAdd()
494 else if (VT == MVT::f128) in getRegForInlineAsmConstraint()
518 if (VT == MVT::f128) in getRegForInlineAsmConstraint()
1195 if (Op0.getValueType() == MVT::f128) in shouldSwapCmpOperands()
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp54 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
184 setOperationAction(ISD::ConstantFP, MVT::f128, Legal); in AArch64TargetLowering()
225 setOperationAction(ISD::FABS, MVT::f128, Expand); in AArch64TargetLowering()
226 setOperationAction(ISD::FADD, MVT::f128, Custom); in AArch64TargetLowering()
227 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
228 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
229 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
230 setOperationAction(ISD::FMA, MVT::f128, Expand); in AArch64TargetLowering()
231 setOperationAction(ISD::FMUL, MVT::f128, Custom); in AArch64TargetLowering()
232 setOperationAction(ISD::FNEG, MVT::f128, Expand); in AArch64TargetLowering()
[all …]
DAArch64CallingConv.td66 CCBitConvertToType<f128>>,
77 CCIfType<[f128], CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 CCIfType<[f128], CCAssignToStack<16, 16>>,
DAArch64RegisterInfo.td167 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
175 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
DAArch64InstrInfo.cpp423 RC->hasType(MVT::f128)) in storeRegToStackSlot()
469 || RC->hasType(MVT::f128)) in loadRegFromStackSlot()
/freebsd-10-stable/contrib/llvm/lib/IR/
DValueTypes.cpp125 case MVT::f128: return "f128"; in getEVTString()
196 case MVT::f128: return Type::getFP128Ty(Context); in getTypeForEVT()
261 case Type::FP128TyID: return MVT(MVT::f128); in getVT()
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.h57 f128 = 11, // This is a 128 bit floating point value enumerator
405 case f128: in getSizeInBits()
477 return MVT::f128; in getFloatingPointVT()
DValueTypes.td33 def f128 : ValueType<128, 11>; // 128-bit floating point value
/freebsd-10-stable/contrib/llvm/utils/TableGen/
DCodeGenTarget.cpp67 case MVT::f128: return "MVT::f128"; in getEnumName()

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