54     addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);  in AArch64TargetLowering()
184   setOperationAction(ISD::ConstantFP, MVT::f128, Legal);  in AArch64TargetLowering()
225   setOperationAction(ISD::FABS,       MVT::f128, Expand);  in AArch64TargetLowering()
226   setOperationAction(ISD::FADD,       MVT::f128, Custom);  in AArch64TargetLowering()
227   setOperationAction(ISD::FCOPYSIGN,  MVT::f128, Expand);  in AArch64TargetLowering()
228   setOperationAction(ISD::FCOS,       MVT::f128, Expand);  in AArch64TargetLowering()
229   setOperationAction(ISD::FDIV,       MVT::f128, Custom);  in AArch64TargetLowering()
230   setOperationAction(ISD::FMA,        MVT::f128, Expand);  in AArch64TargetLowering()
231   setOperationAction(ISD::FMUL,       MVT::f128, Custom);  in AArch64TargetLowering()
232   setOperationAction(ISD::FNEG,       MVT::f128, Expand);  in AArch64TargetLowering()
233   setOperationAction(ISD::FP_EXTEND,  MVT::f128, Expand);  in AArch64TargetLowering()
234   setOperationAction(ISD::FP_ROUND,   MVT::f128, Expand);  in AArch64TargetLowering()
235   setOperationAction(ISD::FPOW,       MVT::f128, Expand);  in AArch64TargetLowering()
236   setOperationAction(ISD::FREM,       MVT::f128, Expand);  in AArch64TargetLowering()
237   setOperationAction(ISD::FRINT,      MVT::f128, Expand);  in AArch64TargetLowering()
238   setOperationAction(ISD::FSIN,       MVT::f128, Expand);  in AArch64TargetLowering()
239   setOperationAction(ISD::FSINCOS,    MVT::f128, Expand);  in AArch64TargetLowering()
240   setOperationAction(ISD::FSQRT,      MVT::f128, Expand);  in AArch64TargetLowering()
241   setOperationAction(ISD::FSUB,       MVT::f128, Custom);  in AArch64TargetLowering()
242   setOperationAction(ISD::FTRUNC,     MVT::f128, Expand);  in AArch64TargetLowering()
243   setOperationAction(ISD::SETCC,      MVT::f128, Custom);  in AArch64TargetLowering()
244   setOperationAction(ISD::BR_CC,      MVT::f128, Custom);  in AArch64TargetLowering()
245   setOperationAction(ISD::SELECT,     MVT::f128, Expand);  in AArch64TargetLowering()
246   setOperationAction(ISD::SELECT_CC,  MVT::f128, Custom);  in AArch64TargetLowering()
247   setOperationAction(ISD::FP_EXTEND,  MVT::f128, Custom);  in AArch64TargetLowering()
273   setTruncStoreAction(MVT::f128, MVT::f64, Expand);  in AArch64TargetLowering()
274   setTruncStoreAction(MVT::f128, MVT::f32, Expand);  in AArch64TargetLowering()
275   setTruncStoreAction(MVT::f128, MVT::f16, Expand);  in AArch64TargetLowering()
1104         SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);  in SaveVarArgRegisters()
1961   if (LHS.getValueType() == MVT::f128) {  in LowerBR_CC()
1964     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);  in LowerBR_CC()
2052   if (Op.getOperand(0).getValueType() != MVT::f128) {  in LowerFP_ROUND()
2067   assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");  in LowerFP_EXTEND()
2078   if (Op.getOperand(0).getValueType() != MVT::f128) {  in LowerFP_TO_INT()
2393   if (Op.getValueType() != MVT::f128) {  in LowerINT_TO_FP()
2445   if (LHS.getValueType() == MVT::f128) {  in LowerSELECT_CC()
2448     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);  in LowerSELECT_CC()
2732   if (LHS.getValueType() == MVT::f128) {  in LowerSETCC()
2735     softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);  in LowerSETCC()
3857   case MVT::f128:  in isFMAFasterThanFMulAndFAdd()