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Searched refs:TII (Results 1 – 25 of 187) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DR600ExpandSpecialInstrs.cpp34 const R600InstrInfo *TII; member in __anon61c9bad10111::R600ExpandSpecialInstrsPass
41 TII(0) { } in R600ExpandSpecialInstrsPass()
59 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); in runOnMachineFunction()
61 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
72 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
73 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction()
76 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
79 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
81 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
95 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I, in runOnMachineFunction()
[all …]
DR600Packetizer.cpp59 const R600InstrInfo *TII; member in __anonfaa48b1f0111::R600PacketizerList
74 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
86 if (TII->isPredicated(BI)) in getPreviousVector()
88 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
91 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
96 if (isTrans || TII->isTransOnly(BI)) { in getPreviousVector()
138 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); in substitutePV()
152 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())), in R600PacketizerList()
153 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
170 if (TII->isVector(*MI)) in isSoloInstruction()
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DR600EmitClauseMarkers.cpp34 const R600InstrInfo *TII; member in __anon9f57832e0111::R600EmitClauseMarkersPass
52 if (TII->isLDSRetInstr(MI->getOpcode())) in OccupiedDwords()
55 if(TII->isVector(*MI) || in OccupiedDwords()
56 TII->isCubeOp(MI->getOpcode()) || in OccupiedDwords()
57 TII->isReductionOp(MI->getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI->getOpcode())) in isALU()
73 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
118 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) in SubstituteKCacheBank()
122 TII->getSrcs(MI); in SubstituteKCacheBank()
123 assert((TII->isALUInstr(MI->getOpcode()) || in SubstituteKCacheBank()
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DR600ClauseMergePass.cpp46 const R600InstrInfo *TII; member in __anonc1348cd10111::R600ClauseMergePass
75 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); in getCFAluSize()
81 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm(); in isCFAluEnabled()
86 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in cleanPotentialDisabledCFAlu()
105 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in mergeIfPossible()
109 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
117 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0); in mergeIfPossible()
119 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0); in mergeIfPossible()
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0); in mergeIfPossible()
133 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1); in mergeIfPossible()
[all …]
DSILowerControlFlow.cpp70 const TargetInstrInfo *TII; member in __anon421bdc630111::SILowerControlFlowPass
94 MachineFunctionPass(ID), TRI(0), TII(0) { } in SILowerControlFlowPass()
155 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
174 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
179 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
191 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
219 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) in Else()
222 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
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DR600ISelLowering.cpp132 const R600InstrInfo *TII = in EmitInstrWithCustomInserter() local
139 if (TII->isLDSRetInstr(MI->getOpcode())) { in EmitInstrWithCustomInserter()
140 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); in EmitInstrWithCustomInserter()
147 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode()))); in EmitInstrWithCustomInserter()
156 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, in EmitInstrWithCustomInserter()
160 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP); in EmitInstrWithCustomInserter()
165 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, in EmitInstrWithCustomInserter()
169 TII->addFlag(NewMI, 0, MO_FLAG_ABS); in EmitInstrWithCustomInserter()
174 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, in EmitInstrWithCustomInserter()
178 TII->addFlag(NewMI, 0, MO_FLAG_NEG); in EmitInstrWithCustomInserter()
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp75 const HexagonInstrInfo *TII = QTM.getInstrInfo(); in runOnMachineFunction() local
96 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) { in runOnMachineFunction()
97 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) { in runOnMachineFunction()
99 TII->get(Hexagon::CONST32_Int_Real), in runOnMachineFunction()
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), in runOnMachineFunction()
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), in runOnMachineFunction()
107 TII->get(Hexagon::STriw_indexed)) in runOnMachineFunction()
111 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), in runOnMachineFunction()
113 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), in runOnMachineFunction()
116 TII->get(Hexagon::STriw_indexed)) in runOnMachineFunction()
[all …]
DHexagonRegisterInfo.cpp131 const HexagonInstrInfo &TII = in eliminateFrameIndex() local
146 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
147 !TII.isSpillPredRegOp(&MI)) { in eliminateFrameIndex()
154 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex()
176 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) { in eliminateFrameIndex()
178 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); in eliminateFrameIndex()
180 TII.get(Hexagon::ADD_rr), in eliminateFrameIndex()
184 TII.get(Hexagon::ADD_ri), in eliminateFrameIndex()
205 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) { in eliminateFrameIndex()
207 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset); in eliminateFrameIndex()
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DHexagonSplitConst32AndConst64.cpp70 const TargetInstrInfo *TII = QTM.getInstrInfo(); in runOnMachineFunction() local
87 TII->get(Hexagon::LO), DestReg).addOperand(Symbol); in runOnMachineFunction()
89 TII->get(Hexagon::HI), DestReg).addOperand(Symbol); in runOnMachineFunction()
100 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol); in runOnMachineFunction()
102 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol); in runOnMachineFunction()
113 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol); in runOnMachineFunction()
115 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol); in runOnMachineFunction()
126 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue); in runOnMachineFunction()
128 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue); in runOnMachineFunction()
145 TII->get(Hexagon::LOi), DestLo).addImm(LowWord); in runOnMachineFunction()
[all …]
DHexagonSplitTFRCondSets.cpp82 const TargetInstrInfo *TII = QTM.getInstrInfo(); in runOnMachineFunction() local
114 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), in runOnMachineFunction()
118 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2), in runOnMachineFunction()
134 TII->get(Hexagon::TFR_cPt), DestReg). in runOnMachineFunction()
139 TII->get(Hexagon::TFRI_cNotPt), DestReg). in runOnMachineFunction()
144 TII->get(Hexagon::TFRI_cNotPt_f), DestReg). in runOnMachineFunction()
160 TII->get(Hexagon::TFRI_cPt), DestReg). in runOnMachineFunction()
165 TII->get(Hexagon::TFRI_cPt_f), DestReg). in runOnMachineFunction()
174 TII->get(Hexagon::TFR_cNotPt), DestReg). in runOnMachineFunction()
190 TII->get(Hexagon::TFRI_cPt), in runOnMachineFunction()
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DHexagonFrameLowering.cpp118 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitPrologue() local
122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0); in emitPrologue()
125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real), in emitPrologue()
127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr), in emitPrologue()
132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes); in emitPrologue()
157 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitEpilogue() local
161 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)); in emitEpilogue()
162 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr), in emitEpilogue()
183 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4)); in emitEpilogue()
198 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)); in emitEpilogue()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsLongBranch.cpp173 const MipsInstrInfo *TII = in initMBBInfo() local
181 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); in initMBBInfo()
220 const MipsInstrInfo *TII = in replaceBranch() local
222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
223 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
257 const MipsInstrInfo *TII = in expandToLongBranch() local
293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
299 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB)) in expandToLongBranch()
300 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)); in expandToLongBranch()
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DMipsSEFrameLowering.cpp128 const MipsSEInstrInfo &TII = in expandLoadCCond() local
137 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
138 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
148 const MipsSEInstrInfo &TII = in expandStoreCCond() local
157 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
159 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
171 const MipsSEInstrInfo &TII = in expandLoadACC() local
183 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); in expandLoadACC()
185 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
187 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp72 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitLoadConstPool() local
78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) in emitLoadConstPool()
95 const TargetInstrInfo &TII, in emitThumbRegPlusImmInReg() argument
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
122 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) in emitThumbRegPlusImmInReg()
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
171 int NumBytes, const TargetInstrInfo &TII, in emitThumbRegPlusImmediate() argument
231 TII, MRI, MIFlags); in emitThumbRegPlusImmediate()
241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate()
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DThumb1FrameLowering.cpp39 const TargetInstrInfo &TII, DebugLoc dl, in emitSPUpdate() argument
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitSPUpdate()
50 const Thumb1InstrInfo &TII = in eliminateCallFramePseudoInstr() local
71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
88 const Thumb1InstrInfo &TII = in emitPrologue() local
109 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
176 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
187 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
[all …]
DARMFrameLowering.cpp86 const ARMBaseInstrInfo &TII, in isCSRestore() argument
109 const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
116 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
119 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
124 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
128 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
139 const ARMBaseInstrInfo &TII = in emitPrologue() local
164 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, in emitPrologue()
169 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
263 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = in emitPrologue() local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) in emitPrologue()
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW) in emitPrologue()
110 const MSP430InstrInfo &TII = in emitEpilogue() local
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW); in emitEpilogue()
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); in emitEpilogue()
161 TII.get(MSP430::SUB16ri), MSP430::SPW) in emitEpilogue()
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW) in emitEpilogue()
191 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in spillCalleeSavedRegisters() local
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreFrameLowering.cpp44 const TargetInstrInfo &TII) { in loadFromStack() argument
51 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) in loadFromStack()
59 const TargetInstrInfo &TII) { in storeToStack() argument
66 BuildMI(MBB, I, dl, TII.get(Opcode)) in storeToStack()
92 const XCoreInstrInfo &TII = in emitPrologue() local
105 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); in emitPrologue()
133 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); in emitPrologue()
138 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); in emitPrologue()
149 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
154 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel); in emitPrologue()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86FrameLowering.cpp149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { in emitSPUpdate() argument
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), in emitSPUpdate()
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
394 const X86InstrInfo &TII = *TM.getInstrInfo(); in emitPrologue() local
455 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)), in emitPrologue()
498 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) in emitPrologue()
505 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) in emitPrologue()
521 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) in emitPrologue()
528 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) in emitPrologue()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp260 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in lowerDynamicAlloc() local
287 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
291 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
295 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
312 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
317 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in lowerDynamicAlloc()
323 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
327 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
337 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
342 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in lowerDynamicAlloc()
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DPPCFrameLowering.cpp93 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { in HandleVRSaveUpdate() argument
141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
167 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
337 const PPCInstrInfo &TII = in emitPrologue() local
364 HandleVRSaveUpdate(MBBI, TII); in emitPrologue()
[all …]
/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DBranchFolding.cpp148 if (!TII->isUnpredicatedTerminator(I)) in OptimizeImpDefsBlock()
182 TII = tii; in OptimizeFunction()
199 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) in OptimizeFunction()
397 TII->ReplaceTailWithBranchTo(OldInst, NewDest); in ReplaceTailWithBranchTo()
411 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1)) in SplitMBBAt()
459 const TargetInstrInfo *TII) { in FixTail() argument
466 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { in FixTail()
469 if (!TII->ReverseBranchCondition(Cond)) { in FixTail()
470 TII->RemoveBranch(*CurMBB); in FixTail()
471 TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond, dl); in FixTail()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp53 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitPrologue() local
89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes, in emitPrologue()
96 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL)) in emitPrologue()
120 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP, in emitPrologue()
133 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL)) in emitPrologue()
149 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes, in emitPrologue()
164 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL)) in emitPrologue()
179 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL)) in emitPrologue()
200 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitEpilogue() local
216 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm)); in emitEpilogue()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp111 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in replaceFI() local
120 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
140 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) in replaceFI()
143 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
177 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in eliminateFrameIndex() local
182 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri)) in eliminateFrameIndex()
185 MI.setDesc(TII.get(SP::STDFri)); in eliminateFrameIndex()
189 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in eliminateFrameIndex() local
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp66 const SystemZInstrInfo &TII = in eliminateFrameIndex() local
87 unsigned OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset); in eliminateFrameIndex()
97 OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset); in eliminateFrameIndex()
110 TII.loadImmediate(MBB, MI, ScratchReg, HighOffset); in eliminateFrameIndex()
116 unsigned LAOpcode = TII.getOpcodeForOffset(SystemZ::LA, HighOffset); in eliminateFrameIndex()
118 BuildMI(MBB, MI, DL, TII.get(LAOpcode),ScratchReg) in eliminateFrameIndex()
123 TII.loadImmediate(MBB, MI, ScratchReg, HighOffset); in eliminateFrameIndex()
124 BuildMI(MBB, MI, DL, TII.get(SystemZ::AGR),ScratchReg) in eliminateFrameIndex()
133 MI->setDesc(TII.get(OpcodeForOffset)); in eliminateFrameIndex()

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