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Searched refs:STI (Results 1 – 25 of 114) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp65 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU, in LLVMCreateDisasmCPU() local
67 if (!STI) in LLVMCreateDisasmCPU()
76 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI); in LLVMCreateDisasmCPU()
94 *MAI, *MII, *MRI, *STI); in LLVMCreateDisasmCPU()
101 STI, MII, Ctx, DisAsm, IP); in LLVMCreateDisasmCPU()
190 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); in getItineraryLatency() local
191 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU()); in getItineraryLatency()
209 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); in getLatency() local
210 const MCSchedModel *SCModel = STI->getSchedModel(); in getLatency()
233 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc, in getLatency()
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/freebsd-10-stable/contrib/llvm/include/llvm/MC/
DMCDisassembler.h59 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0), in MCDisassembler() argument
61 STI(STI), Symbolizer(0), in MCDisassembler()
104 const MCSubtargetInfo &STI;
134 const MCSubtargetInfo& getSubtargetInfo() const { return STI; } in getSubtargetInfo()
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp36 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in MipsDisassemblerBase() argument
38 MCDisassembler(STI), RegInfo(Info), in MipsDisassemblerBase()
39 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} in MipsDisassemblerBase()
60 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in MipsDisassembler() argument
62 MipsDisassemblerBase(STI, Info, bigEndian) { in MipsDisassembler()
63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; in MipsDisassembler()
81 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in Mips64Disassembler() argument
83 MipsDisassemblerBase(STI, Info, bigEndian) {} in Mips64Disassembler()
273 const MCSubtargetInfo &STI) { in createMipsDisassembler() argument
274 return new MipsDisassembler(STI, T.createMCRegInfo(""), true); in createMipsDisassembler()
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/freebsd-10-stable/contrib/llvm/lib/Target/R600/MCTargetDesc/
DAMDGPUMCTargetDesc.cpp70 const MCSubtargetInfo &STI) { in createAMDGPUMCInstPrinter() argument
76 const MCSubtargetInfo &STI, in createAMDGPUMCCodeEmitter() argument
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { in createAMDGPUMCCodeEmitter()
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); in createAMDGPUMCCodeEmitter()
81 return createR600MCCodeEmitter(MCII, MRI, STI); in createAMDGPUMCCodeEmitter()
DR600MCCodeEmitter.cpp37 const MCSubtargetInfo &STI; member in __anona00df5f70111::R600MCCodeEmitter
43 : MCII(mcii), MRI(mri), STI(sti) { } in R600MCCodeEmitter()
85 const MCSubtargetInfo &STI) { in createR600MCCodeEmitter() argument
86 return new R600MCCodeEmitter(MCII, MRI, STI); in createR600MCCodeEmitter()
101 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { in EncodeInstruction()
134 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && in EncodeInstruction()
DAMDGPUMCTargetDesc.h36 const MCSubtargetInfo &STI);
40 const MCSubtargetInfo &STI,
/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DTargetSchedule.cpp58 STI = sti; in init()
60 STI->initInstrItins(InstrItins); in init()
117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
193 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
245 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeInstrLatency()
280 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc), in computeOutputLatency()
281 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) { in computeOutputLatency()
DLLVMTargetMachine.cpp167 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitFile() local
174 MII, MRI, STI); in addPassesToEmitFile()
179 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context); in addPassesToEmitFile()
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, in addPassesToEmitFile()
270 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitMC() local
272 STI, *Ctx); in addPassesToEmitMC()
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), in ARMBaseRegisterInfo()
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
54 const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCalleeSavedRegs()
66 if (STI.isMClass()) { in getCalleeSavedRegs()
89 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCallPreservedMask()
111 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getThisReturnPreservedMask()
130 if (STI.isR9Reserved()) in getReservedRegs()
133 if (!STI.hasVFP3() || STI.hasD16()) { in getReservedRegs()
192 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); in getRegPressureLimit()
282 if (!STI.isLikeA9()) in avoidWriteAfterWrite()
DThumb1InstrInfo.cpp24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) in Thumb1InstrInfo() argument
25 : ARMBaseInstrInfo(STI), RI(STI) { in Thumb1InstrInfo()
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DTargetSchedule.h37 const TargetSubtargetInfo *STI; variable
44 TargetSchedModel(): STI(0), TII(0) {} in TargetSchedModel()
107 return STI->getWriteProcResBegin(SC); in getWriteProcResBegin()
110 return STI->getWriteProcResEnd(SC); in getWriteProcResEnd()
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp268 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I]; in ehDataReg()
283 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; in emitPrologue()
284 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; in emitPrologue()
285 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in emitPrologue()
286 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in emitPrologue()
335 if (!STI.isLittle()) in emitPrologue()
351 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue()
399 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; in emitEpilogue()
400 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; in emitEpilogue()
401 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in emitEpilogue()
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DMipsSEFrameLowering.h23 explicit MipsSEFrameLowering(const MipsSubtarget &STI) in MipsSEFrameLowering() argument
24 : MipsFrameLowering(STI, STI.stackAlignment()) {} in MipsSEFrameLowering()
DMips16FrameLowering.h22 explicit Mips16FrameLowering(const MipsSubtarget &STI) in Mips16FrameLowering() argument
23 : MipsFrameLowering(STI, STI.stackAlignment()) {} in Mips16FrameLowering()
DMipsSEInstrInfo.cpp353 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in adjustStackPtr() local
355 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in adjustStackPtr()
356 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; in adjustStackPtr()
373 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in loadImmediate() local
375 unsigned Size = STI.isABI_N64() ? 64 : 32; in loadImmediate()
376 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; in loadImmediate()
377 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate()
378 const TargetRegisterClass *RC = STI.isABI_N64() ? in loadImmediate()
546 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in expandEhReturn() local
547 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in expandEhReturn()
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DMipsFrameLowering.h26 const MipsSubtarget &STI;
30 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {} in MipsFrameLowering()
/freebsd-10-stable/sys/i386/i386/
Ddb_disasm.c85 #define STI 32 /* FP stack */ macro
430 /*0*/ { "fadd", SNGL, op2(STI,ST), 0 },
431 /*1*/ { "fmul", SNGL, op2(STI,ST), 0 },
432 /*2*/ { "fcom", SNGL, op2(STI,ST), 0 },
433 /*3*/ { "fcomp", SNGL, op2(STI,ST), 0 },
434 /*4*/ { "fsub", SNGL, op2(STI,ST), 0 },
435 /*5*/ { "fsubr", SNGL, op2(STI,ST), 0 },
436 /*6*/ { "fdiv", SNGL, op2(STI,ST), 0 },
437 /*7*/ { "fdivr", SNGL, op2(STI,ST), 0 },
441 /*0*/ { "fld", SNGL, op1(STI), 0 },
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/freebsd-10-stable/contrib/llvm/include/llvm/Support/
DTargetRegistry.h110 typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
114 const MCSubtargetInfo &STI);
120 const MCSubtargetInfo &STI);
123 const MCSubtargetInfo &STI,
368 MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, in createMCAsmParser() argument
373 return MCAsmParserCtorFn(STI, Parser, MII); in createMCAsmParser()
384 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const { in createMCDisassembler() argument
387 return MCDisassemblerCtorFn(*this, STI); in createMCDisassembler()
394 const MCSubtargetInfo &STI) const { in createMCInstPrinter() argument
397 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, STI); in createMCInstPrinter()
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86FrameLowering.cpp402 bool Is64Bit = STI.is64Bit(); in emitPrologue()
403 bool IsLP64 = STI.isTarget64BitLP64(); in emitPrologue()
404 bool IsWin64 = STI.isTargetWin64(); in emitPrologue()
405 bool UseLEA = STI.useLeaForSP(); in emitPrologue()
609 if (NumBytes >= 4096 && STI.isOSWindows() && !STI.isTargetEnvMacho()) { in emitPrologue()
614 if (STI.isTargetCygMing()) in emitPrologue()
620 } else if (STI.isTargetCygMing()) in emitPrologue()
722 bool Is64Bit = STI.is64Bit(); in emitEpilogue()
723 bool IsLP64 = STI.isTarget64BitLP64(); in emitEpilogue()
724 bool UseLEA = STI.useLeaForSP(); in emitEpilogue()
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/freebsd-10-stable/sys/amd64/amd64/
Ddb_disasm.c99 #define STI 32 /* FP stack */ macro
504 /*0*/ { "fadd", SNGL, op2(STI,ST), 0 },
505 /*1*/ { "fmul", SNGL, op2(STI,ST), 0 },
506 /*2*/ { "fcom", SNGL, op2(STI,ST), 0 },
507 /*3*/ { "fcomp", SNGL, op2(STI,ST), 0 },
508 /*4*/ { "fsub", SNGL, op2(STI,ST), 0 },
509 /*5*/ { "fsubr", SNGL, op2(STI,ST), 0 },
510 /*6*/ { "fdiv", SNGL, op2(STI,ST), 0 },
511 /*7*/ { "fdivr", SNGL, op2(STI,ST), 0 },
515 /*0*/ { "fld", SNGL, op1(STI), 0 },
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.cpp33 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, in getMCRDeprecationInfo() argument
35 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops && in getMCRDeprecationInfo()
65 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, in getITDeprecationInfo() argument
67 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && in getITDeprecationInfo()
262 const MCSubtargetInfo &STI) { in createARMMCInstPrinter() argument
264 return new ARMInstPrinter(MAI, MII, MRI, STI); in createARMMCInstPrinter()
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp40 const MCSubtargetInfo &STI; member in __anoncf1217990111::MipsMCCodeEmitter
47 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) { in MipsMCCodeEmitter()
48 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; in MipsMCCodeEmitter()
131 const MCSubtargetInfo &STI, in createMipsMCCodeEmitterEB() argument
134 return new MipsMCCodeEmitter(MCII, Ctx, STI, false); in createMipsMCCodeEmitterEB()
139 const MCSubtargetInfo &STI, in createMipsMCCodeEmitterEL() argument
142 return new MipsMCCodeEmitter(MCII, Ctx, STI, true); in createMipsMCCodeEmitterEL()
247 if (STI.getFeatureBits() & Mips::FeatureMicroMips) { in EncodeInstruction()
/freebsd-10-stable/contrib/llvm/tools/llvm-mc/
Dllvm-mc.cpp322 MCAsmInfo &MAI, MCSubtargetInfo &STI, MCInstrInfo &MCII) { in AssembleInput() argument
325 OwningPtr<MCTargetAsmParser> TAP(TheTarget->createMCAsmParser(STI, *Parser, MCII)); in AssembleInput()
425 STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); in main() local
430 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI); in main()
434 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); in main()
448 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); in main()
462 Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI, *MCII); in main()
479 Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str, in main()
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp35 SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : in SparcDisassembler() argument
36 MCDisassembler(STI), RegInfo(Info) in SparcDisassembler()
61 const MCSubtargetInfo &STI) { in createSparcDisassembler() argument
62 return new SparcDisassembler(STI, T.createMCRegInfo("")); in createSparcDisassembler()
220 this, STI); in getInstruction()
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp36 const MCSubtargetInfo &STI; member in __anonc78b158a0111::PPCMCCodeEmitter
43 : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) { in PPCMCCodeEmitter()
111 const MCSubtargetInfo &STI, in createPPCMCCodeEmitter() argument
113 return new PPCMCCodeEmitter(MCII, STI, Ctx); in createPPCMCCodeEmitter()

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