36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,  in MipsDisassemblerBase()  argument
38     MCDisassembler(STI), RegInfo(Info),  in MipsDisassemblerBase()
39     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}  in MipsDisassemblerBase()
60   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,  in MipsDisassembler()  argument
62     MipsDisassemblerBase(STI, Info, bigEndian) {  in MipsDisassembler()
63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;  in MipsDisassembler()
81   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,  in Mips64Disassembler()  argument
83     MipsDisassemblerBase(STI, Info, bigEndian) {}  in Mips64Disassembler()
273                        const MCSubtargetInfo &STI) {  in createMipsDisassembler()  argument
274   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);  in createMipsDisassembler()
279                        const MCSubtargetInfo &STI) {  in createMipselDisassembler()  argument
280   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);  in createMipselDisassembler()
285                        const MCSubtargetInfo &STI) {  in createMips64Disassembler()  argument
286   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);  in createMips64Disassembler()
291                        const MCSubtargetInfo &STI) {  in createMips64elDisassembler()  argument
292   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);  in createMips64elDisassembler()
371                                this, STI);  in getInstruction()
381                              this, STI);  in getInstruction()
406                              this, STI);  in getInstruction()
413                              this, STI);  in getInstruction()