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Searched refs:SDValue (Results 1 – 25 of 109) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h87 SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
91 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedIntegers;
95 SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
99 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;
103 SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
107 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> SplitVectors;
111 SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
115 SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
139 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
146 void AnalyzeNewValue(SDValue &Val);
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/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DSelectionDAG.h186 SDValue Root;
332 const SDValue &getRoot() const { return Root; }
336 SDValue getEntryNode() const {
337 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
342 const SDValue &setRoot(SDValue N) {
408 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
409 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
410 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
411 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
412 SDValue getTargetConstant(uint64_t Val, EVT VT) {
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/freebsd-10-stable/contrib/llvm/include/llvm/Target/
DTargetSelectionDAGInfo.h56 virtual SDValue
58 SDValue Chain, in EmitTargetCodeForMemcpy()
59 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy()
60 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy()
64 return SDValue(); in EmitTargetCodeForMemcpy()
73 virtual SDValue
75 SDValue Chain, in EmitTargetCodeForMemmove()
76 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove()
77 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
80 return SDValue(); in EmitTargetCodeForMemmove()
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/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCISelLowering.h333 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
354 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
355 SDValue &Offset,
362 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
369 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
374 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
381 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
386 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
389 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
391 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DAMDGPUISelLowering.h28 void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
29 SmallVectorImpl<SDValue> &Args,
31 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
37 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
40 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
41 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
49 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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DSIISelLowering.h24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
28 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
30 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
31 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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DR600ISelLowering.h29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
30 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
32 SmallVectorImpl<SDValue> &Results,
34 virtual SDValue LowerFormalArguments(
35 SDValue Chain,
40 SmallVectorImpl<SDValue> &InVals) const;
48 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
53 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
56 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreISelLowering.h90 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
97 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
102 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
121 SDValue LowerCCCArguments(SDValue Chain,
126 SmallVectorImpl<SDValue> &InVals) const;
127 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
131 const SmallVectorImpl<SDValue> &OutVals,
134 SmallVectorImpl<SDValue> &InVals) const;
135 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
139 SmallVectorImpl<SDValue> &InVals) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h215 SDValue LowerFormalArguments(SDValue Chain,
219 SmallVectorImpl<SDValue> &InVals) const;
221 SDValue LowerReturn(SDValue Chain,
224 const SmallVectorImpl<SDValue> &OutVals,
227 SDValue LowerCall(CallLoweringInfo &CLI,
228 SmallVectorImpl<SDValue> &InVals) const;
230 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
234 SmallVectorImpl<SDValue> &InVals) const;
236 bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &Res) const;
238 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86ISelLowering.h509 bool isZeroNode(SDValue Elt);
540 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
583 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
588 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
592 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
604 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
621 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
629 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
635 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
652 virtual void LowerAsmOperandForConstraint(SDValue Op,
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/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
40 SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
43 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
44 SDValue &Offset) const;
46 virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
47 SDValue &Offset) const;
49 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
50 SDValue &Offset) const;
52 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
53 SDValue &Offset) const;
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DMipsISelDAGToDAG.h57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
62 virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
63 SDValue &Offset) const;
66 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const;
70 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
71 SDValue &Offset) const;
73 virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
74 SDValue &Offset) const;
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DMipsISelDAGToDAG.cpp66 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
67 SDValue &Offset) const { in selectAddrRegImm()
72 bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, in selectAddrRegReg()
73 SDValue &Offset) const { in selectAddrRegReg()
78 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
79 SDValue &Offset) const { in selectAddrDefault()
84 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
85 SDValue &Offset) const { in selectIntAddr()
90 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, in selectIntAddrMM()
91 SDValue &Offset) const { in selectIntAddrMM()
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DMipsISelLowering.h220 SmallVectorImpl<SDValue> &Results,
224 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
229 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
239 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
251 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
258 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, in getAddrLocal()
262 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
264 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
268 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
278 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, in getAddrGlobal()
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/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.h29 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
30 SDValue Dst, SDValue Src,
31 SDValue Size, unsigned Align,
37 virtual SDValue
39 SDValue Chain, SDValue Dst, SDValue Byte,
40 SDValue Size, unsigned Align, bool IsVolatile,
43 virtual std::pair<SDValue, SDValue>
44 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
45 SDValue Src1, SDValue Src2, SDValue Size,
49 virtual std::pair<SDValue, SDValue>
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DSystemZSelectionDAGInfo.cpp33 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem()
34 unsigned Loop, SDValue Chain, SDValue Dst, in emitMemMem()
35 SDValue Src, uint64_t Size) { in emitMemMem()
56 SDValue SystemZSelectionDAGInfo::
57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy()
58 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, in EmitTargetCodeForMemcpy()
63 return SDValue(); in EmitTargetCodeForMemcpy()
68 return SDValue(); in EmitTargetCodeForMemcpy()
74 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore()
75 SDValue Dst, uint64_t ByteVal, uint64_t Size, in memsetStore()
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DSystemZISelLowering.h220 LowerAsmOperandForConstraint(SDValue Op,
222 std::vector<SDValue> &Ops,
227 virtual SDValue LowerOperation(SDValue Op,
231 virtual SDValue
232 LowerFormalArguments(SDValue Chain,
236 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
237 virtual SDValue
239 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
241 virtual SDValue
242 LowerReturn(SDValue Chain,
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DSystemZISelDAGToDAG.cpp56 SDValue Base;
58 SDValue Index;
113 RxSBGOperands(unsigned Op, SDValue N) in RxSBGOperands()
121 SDValue Input;
132 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { in getImm()
149 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
153 SDValue &Base, SDValue &Disp) const;
155 SDValue &Base, SDValue &Disp, SDValue &Index) const;
160 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
161 SDValue &Base, SDValue &Disp) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcISelLowering.h58 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
63 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
79 void LowerAsmOperandForConstraint(SDValue Op,
81 std::vector<SDValue> &Ops,
92 virtual SDValue
93 LowerFormalArguments(SDValue Chain,
98 SmallVectorImpl<SDValue> &InVals) const;
99 SDValue LowerFormalArguments_32(SDValue Chain,
104 SmallVectorImpl<SDValue> &InVals) const;
105 SDValue LowerFormalArguments_64(SDValue Chain,
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/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430ISelLowering.h79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMISelLowering.h245 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
250 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
270 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
271 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
287 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
312 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
313 SDValue &Offset,
321 SDValue &Base, SDValue &Offset,
325 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
349 virtual void LowerAsmOperandForConstraint(SDValue Op,
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DARMISelDAGToDAG.cpp84 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm()
92 bool isShifterOpProfitable(const SDValue &Shift,
94 bool SelectRegShifterOperand(SDValue N, SDValue &A,
95 SDValue &B, SDValue &C,
97 bool SelectImmShifterOperand(SDValue N, SDValue &A,
98 SDValue &B, bool CheckProfitability = true);
99 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A, in SelectShiftRegShifterOperand()
100 SDValue &B, SDValue &C) { in SelectShiftRegShifterOperand()
104 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A, in SelectShiftImmShifterOperand()
105 SDValue &B) { in SelectShiftImmShifterOperand()
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h84 IsEligibleForTailCallOptimization(SDValue Callee,
91 const SmallVectorImpl<SDValue> &OutVals,
100 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFormalArguments(SDValue Chain,
112 SmallVectorImpl<SDValue> &InVals) const;
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DHexagonISelDAGToDAG.cpp67 inline bool foldGlobalAddress(SDValue &N, SDValue &R);
68 inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
69 bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
70 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
71 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
72 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
73 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
74 bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
75 bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
76 bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
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/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h56 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
71 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm()
76 bool SelectDirectAddr(SDValue N, SDValue &Address);
78 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
79 SDValue &Offset, MVT mvt);
80 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
81 SDValue &Offset);
82 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
83 SDValue &Offset);
85 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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