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Searched refs:ProcModel (Results 1 – 3 of 3) sorted by relevance

/freebsd-10-stable/contrib/llvm/utils/TableGen/
DSubtargetEmitter.cpp84 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
87 const CodeGenProcModel &ProcModel);
89 const CodeGenProcModel &ProcModel);
91 const CodeGenProcModel &ProcModel);
92 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
442 const CodeGenProcModel &ProcModel = *PI; in EmitStageAndOperandCycleData() local
450 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
453 const std::string &Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
456 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
462 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
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DCodeGenSchedule.cpp429 const CodeGenProcModel &ProcModel) const { in expandRWSeqForProc()
438 if (&getProcModel(ModelDef) != &ProcModel) in expandRWSeqForProc()
443 "defined for processor " + ProcModel.ModelName + in expandRWSeqForProc()
449 RWSeq, IsRead,ProcModel); in expandRWSeqForProc()
461 expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel); in expandRWSeqForProc()
572 const CodeGenProcModel &ProcModel = in collectSchedClasses() local
574 ProcIndices.push_back(ProcModel.Index); in collectSchedClasses()
575 dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName; in collectSchedClasses()
788 CodeGenProcModel &ProcModel = *PI; in collectProcItins() local
789 if (!ProcModel.hasItineraries()) in collectProcItins()
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DCodeGenSchedule.h342 const CodeGenProcModel &ProcModel) const;