84   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
87                              const CodeGenProcModel &ProcModel);
89                           const CodeGenProcModel &ProcModel);
91                            const CodeGenProcModel &ProcModel);
92   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
442     const CodeGenProcModel &ProcModel = *PI;  in EmitStageAndOperandCycleData()  local
450     if (!ProcModel.hasItineraries())  in EmitStageAndOperandCycleData()
453     const std::string &Name = ProcModel.ItinsDef->getName();  in EmitStageAndOperandCycleData()
456     assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");  in EmitStageAndOperandCycleData()
462       Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];  in EmitStageAndOperandCycleData()
622 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,  in EmitProcessorResources()  argument
624   char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';  in EmitProcessorResources()
628      << ProcModel.ModelName << "ProcResources" << "[] = {\n"  in EmitProcessorResources()
631   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {  in EmitProcessorResources()
632     Record *PRDef = ProcModel.ProcResourceDefs[i];  in EmitProcessorResources()
649           PRDef->getValueAsDef("Super"), ProcModel);  in EmitProcessorResources()
650         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);  in EmitProcessorResources()
672   const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {  in FindWriteResources()  argument
686       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)  in FindWriteResources()
691                     "defined for processor " + ProcModel.ModelName +  in FindWriteResources()
700   for (RecIter WRI = ProcModel.WriteResDefs.begin(),  in FindWriteResources()
701          WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {  in FindWriteResources()
709                       ProcModel.ModelName);  in FindWriteResources()
717     PrintFatalError(ProcModel.ModelDef->getLoc(),  in FindWriteResources()
727                                           const CodeGenProcModel &ProcModel) {  in FindReadAdvance()  argument
740       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)  in FindReadAdvance()
745                     "defined for processor " + ProcModel.ModelName +  in FindReadAdvance()
754   for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),  in FindReadAdvance()
755          RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {  in FindReadAdvance()
763                       ProcModel.ModelName);  in FindReadAdvance()
771     PrintFatalError(ProcModel.ModelDef->getLoc(),  in FindReadAdvance()
830 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,  in GenSchedClassTables()  argument
833   if (!ProcModel.hasInstrSchedModel())  in GenSchedClassTables()
861                                 TI->ProcIndices.end(), ProcModel.Index);  in GenSchedClassTables()
878                                 SCI->ProcIndices.end(), ProcModel.Index);  in GenSchedClassTables()
891         if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {  in GenSchedClassTables()
905       for (RecIter II = ProcModel.ItinRWDefs.begin(),  in GenSchedClassTables()
906              IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {  in GenSchedClassTables()
916         DEBUG(dbgs() << ProcModel.ModelName  in GenSchedClassTables()
928                                      ProcModel);  in GenSchedClassTables()
947           FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);  in GenSchedClassTables()
964         ExpandProcResources(PRVec, Cycles, ProcModel);  in GenSchedClassTables()
969           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);  in GenSchedClassTables()
995         FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);  in GenSchedClassTables()