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Searched refs:MVT (Results 1 – 25 of 173) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp188 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = { in getCastInstrCost()
190 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
191 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
192 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
197 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); in getCastInstrCost()
212 static const TypeConversionCostTblEntry<MVT::SimpleValueType> in getCastInstrCost()
214 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
215 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
216 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
217 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
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DARMISelDAGToDAG.cpp85 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
135 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); in SelectCMOVPred()
136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
283 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
396 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
398 CurDAG->getConstant(Srl_imm+TZ, MVT::i32)); in PreprocessISelDAG()
399 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32, in PreprocessISelDAG()
400 Srl, CurDAG->getConstant(And_imm, MVT::i32)); in PreprocessISelDAG()
401 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32, in PreprocessISelDAG()
402 N1, CurDAG->getConstant(TZ, MVT::i32)); in PreprocessISelDAG()
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/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp175 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty); in getArithmeticInstrCost()
180 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = { in getArithmeticInstrCost()
183 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
184 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
185 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
186 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
187 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
188 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
189 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
190 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
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DX86ISelLowering.cpp225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; in resetOperationActions()
287 addRegisterClass(MVT::i8, &X86::GR8RegClass); in resetOperationActions()
288 addRegisterClass(MVT::i16, &X86::GR16RegClass); in resetOperationActions()
289 addRegisterClass(MVT::i32, &X86::GR32RegClass); in resetOperationActions()
291 addRegisterClass(MVT::i64, &X86::GR64RegClass); in resetOperationActions()
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in resetOperationActions()
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in resetOperationActions()
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in resetOperationActions()
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in resetOperationActions()
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand); in resetOperationActions()
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/freebsd-10-stable/contrib/llvm/lib/IR/
DValueTypes.cpp115 case MVT::i1: return "i1"; in getEVTString()
116 case MVT::i8: return "i8"; in getEVTString()
117 case MVT::i16: return "i16"; in getEVTString()
118 case MVT::i32: return "i32"; in getEVTString()
119 case MVT::i64: return "i64"; in getEVTString()
120 case MVT::i128: return "i128"; in getEVTString()
121 case MVT::f16: return "f16"; in getEVTString()
122 case MVT::f32: return "f32"; in getEVTString()
123 case MVT::f64: return "f64"; in getEVTString()
124 case MVT::f80: return "f80"; in getEVTString()
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/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.h33 class MVT {
163 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {} in MVT() function
164 MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT() function
166 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
167 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
168 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
169 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
170 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
171 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
175 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && in isFloatingPoint()
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/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp219 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
237 MVT ScalarVT = SimpleVT.getScalarType(); in SelectLoad()
254 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in SelectLoad()
258 case MVT::i8: in SelectLoad()
261 case MVT::i16: in SelectLoad()
264 case MVT::i32: in SelectLoad()
267 case MVT::i64: in SelectLoad()
270 case MVT::f32: in SelectLoad()
273 case MVT::f64: in SelectLoad()
282 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); in SelectLoad()
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DNVPTXISelLowering.cpp50 static bool IsPTXVectorType(MVT VT) { in IsPTXVectorType()
54 case MVT::v2i1: in IsPTXVectorType()
55 case MVT::v4i1: in IsPTXVectorType()
56 case MVT::v2i8: in IsPTXVectorType()
57 case MVT::v4i8: in IsPTXVectorType()
58 case MVT::v2i16: in IsPTXVectorType()
59 case MVT::v4i16: in IsPTXVectorType()
60 case MVT::v2i32: in IsPTXVectorType()
61 case MVT::v4i32: in IsPTXVectorType()
62 case MVT::v2i64: in IsPTXVectorType()
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/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DTargetLoweringBase.cpp412 if (OpVT == MVT::f32) { in getFPEXT()
413 if (RetVT == MVT::f64) in getFPEXT()
415 if (RetVT == MVT::f128) in getFPEXT()
417 } else if (OpVT == MVT::f64) { in getFPEXT()
418 if (RetVT == MVT::f128) in getFPEXT()
428 if (RetVT == MVT::f32) { in getFPROUND()
429 if (OpVT == MVT::f64) in getFPROUND()
431 if (OpVT == MVT::f80) in getFPROUND()
433 if (OpVT == MVT::f128) in getFPROUND()
435 if (OpVT == MVT::ppcf128) in getFPROUND()
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp63 CC_Hexagon(unsigned ValNo, MVT ValVT,
64 MVT LocVT, CCValAssign::LocInfo LocInfo,
68 CC_Hexagon32(unsigned ValNo, MVT ValVT,
69 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 CC_Hexagon64(unsigned ValNo, MVT ValVT,
74 MVT LocVT, CCValAssign::LocInfo LocInfo,
78 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
79 MVT LocVT, CCValAssign::LocInfo LocInfo,
83 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
84 MVT LocVT, CCValAssign::LocInfo LocInfo,
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DHexagonISelDAGToDAG.cpp122 return CurDAG->getTargetConstant(bitPos, MVT::i32); in XformMskToBitPosU5Imm()
150 return CurDAG->getTargetConstant( - Imm, MVT::i32); in XformM5ToU5Imm()
158 return CurDAG->getTargetConstant(Imm - 1, MVT::i8); in XformU7ToU7M1Imm()
163 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); in XformSToSM1Imm()
169 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); in XformUToUM1Imm()
365 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) { in OffsetFitsS11()
368 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) { in OffsetFitsS11()
371 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) { in OffsetFitsS11()
374 if (MemType == MVT::i8 && isInt<11>(Offset)) { in OffsetFitsS11()
397 MVT PointerTy = getTargetLowering()->getPointerTy(); in SelectBaseOffsetLoad()
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/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DAMDILISelLowering.cpp43 (int)MVT::i8, in InitAMDILLowering()
44 (int)MVT::i16, in InitAMDILLowering()
45 (int)MVT::i32, in InitAMDILLowering()
46 (int)MVT::f32, in InitAMDILLowering()
47 (int)MVT::f64, in InitAMDILLowering()
48 (int)MVT::i64, in InitAMDILLowering()
49 (int)MVT::v2i8, in InitAMDILLowering()
50 (int)MVT::v4i8, in InitAMDILLowering()
51 (int)MVT::v2i16, in InitAMDILLowering()
52 (int)MVT::v4i16, in InitAMDILLowering()
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DAMDGPUISelLowering.cpp32 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, in allocateStack()
50 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
54 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
55 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
56 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
57 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
58 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
59 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
60 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
61 setOperationAction(ISD::FROUND, MVT::f32, Legal); in AMDGPUTargetLowering()
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DSIISelLowering.cpp34 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass); in SITargetLowering()
35 addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass); in SITargetLowering()
37 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
38 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
40 addRegisterClass(MVT::i32, &AMDGPU::VSrc_32RegClass); in SITargetLowering()
41 addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass); in SITargetLowering()
43 addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass); in SITargetLowering()
44 addRegisterClass(MVT::v2i32, &AMDGPU::VSrc_64RegClass); in SITargetLowering()
45 addRegisterClass(MVT::v2f32, &AMDGPU::VSrc_64RegClass); in SITargetLowering()
47 addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass); in SITargetLowering()
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DR600ISelLowering.cpp32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
42 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
43 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
44 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
45 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
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/freebsd-10-stable/contrib/llvm/utils/TableGen/
DCodeGenTarget.cpp38 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
42 std::string llvm::getName(MVT::SimpleValueType T) { in getName()
44 case MVT::Other: return "UNKNOWN"; in getName()
45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
46 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
51 std::string llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
53 case MVT::Other: return "MVT::Other"; in getEnumName()
54 case MVT::i1: return "MVT::i1"; in getEnumName()
55 case MVT::i8: return "MVT::i8"; in getEnumName()
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/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp111 virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
143 bool isTypeLegal(Type *Ty, MVT &VT);
144 bool isLoadTypeLegal(Type *Ty, MVT &VT);
147 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
150 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
152 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
154 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
156 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
157 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
158 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
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DPPCISelDAGToDAG.cpp75 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
81 return CurDAG->getTargetConstant(Imm, MVT::i64); in getI64Imm()
263 if (PPCLowering.getPointerTy() == MVT::i32) { in getGlobalBaseReg()
286 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { in isInt64Immediate()
361 if (N->getValueType(0) != MVT::i32) in isRotateAndMask()
463 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); in SelectBitfieldInsert()
476 if (LHS.getValueType() == MVT::i32) { in SelectCC()
482 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, in SelectCC()
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DPPCISelLowering.cpp75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in PPCTargetLowering()
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in PPCTargetLowering()
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_f64()
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_f64()
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
94 if (LocVT == MVT::i64 && Offset < 6*8) in CC_Sparc64_Full()
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/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp73 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
90 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
91 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in XCoreTargetLowering()
92 setOperationAction(ISD::ADDC, MVT::i32, Expand); in XCoreTargetLowering()
93 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
94 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
95 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
98 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in XCoreTargetLowering()
101 setOperationAction(ISD::ADD, MVT::i64, Custom); in XCoreTargetLowering()
102 setOperationAction(ISD::SUB, MVT::i64, Custom); in XCoreTargetLowering()
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp47 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass); in AArch64TargetLowering()
48 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass); in AArch64TargetLowering()
51 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
52 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
53 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
54 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
59 addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
60 addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
61 addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
62 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
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/freebsd-10-stable/contrib/llvm/include/llvm/Target/
DTargetLowering.h155 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
158 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
165 virtual MVT getVectorIdxTy() const { in getVectorIdxTy()
228 MVT::SimpleValueType getCmpLibcallReturnType() const;
258 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
271 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
278 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
294 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
301 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
305 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
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/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsISelLowering.cpp216 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
217 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
218 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
221 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in MipsTargetLowering()
222 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in MipsTargetLowering()
228 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in MipsTargetLowering()
231 setOperationAction(ISD::BR_JT, MVT::Other, Custom); in MipsTargetLowering()
232 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in MipsTargetLowering()
233 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in MipsTargetLowering()
234 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in MipsTargetLowering()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MSP430TargetLowering()
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
[all …]

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