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/freebsd-10-stable/contrib/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp29 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, in EmitAnyX86InstComments() argument
35 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
38 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
39 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
40 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
41 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
46 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
47 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
48 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
54 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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DX86ATTInstPrinter.h30 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
37 void printInstruction(const MCInst *MI, raw_ostream &OS);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
41 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
42 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
45 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
47 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printopaquemem() argument
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DX86IntelInstPrinter.h31 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
41 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printopaquemem() argument
46 printMemReference(MI, OpNo, O); in printopaquemem()
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h29 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
33 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
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DARMInstPrinter.cpp75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
77 unsigned Opcode = MI->getOpcode(); in printInst()
85 switch (MI->getOperand(0).getImm()) { in printInst()
98 printInstruction(MI, O); in printInst()
102 printPredicateOperand(MI, 1, O); in printInst()
111 const MCOperand &Dst = MI->getOperand(0); in printInst()
112 const MCOperand &MO1 = MI->getOperand(1); in printInst()
113 const MCOperand &MO2 = MI->getOperand(2); in printInst()
114 const MCOperand &MO3 = MI->getOperand(3); in printInst()
117 printSBitModifierOperand(MI, 6, O); in printInst()
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
104 unsigned getAddrModeSBit(const MachineInstr &MI,
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DA15SDOptimizer.cpp65 bool runOnInstruction(MachineInstr *MI);
105 bool hasPartialWrite(MachineInstr *MI);
106 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
113 MachineInstr *elideCopies(MachineInstr *MI);
114 void elideCopiesAndPHIs(MachineInstr *MI,
120 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
121 unsigned optimizeSDPattern(MachineInstr *MI);
127 void eraseInstrWithNoUses(MachineInstr *MI);
164 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane() local
165 if (!MI) return ARM::ssub_0; in getPrefSPRLane()
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/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp49 bool LowerSubregToReg(MachineInstr *MI);
50 bool LowerCopy(MachineInstr *MI);
52 void TransferImplicitDefs(MachineInstr *MI);
66 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
67 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
70 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
71 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
78 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
79 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
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DTargetInstrInfo.cpp61 MachineBasicBlock::iterator MI) const { in insertNoop()
119 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI, in commuteInstruction() argument
121 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
123 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction()
127 if (!findCommutedOpIndices(MI, Idx1, Idx2)) { in commuteInstruction()
130 Msg << "Don't know how to commute: " << *MI; in commuteInstruction()
134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction()
136 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction()
137 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction()
138 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction()
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/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DSILowerControlFlow.cpp75 void SkipIfDead(MachineInstr &MI);
77 void If(MachineInstr &MI);
78 void Else(MachineInstr &MI);
79 void Break(MachineInstr &MI);
80 void IfBreak(MachineInstr &MI);
81 void ElseBreak(MachineInstr &MI);
82 void Loop(MachineInstr &MI);
83 void EndCf(MachineInstr &MI);
85 void Kill(MachineInstr &MI);
86 void Branch(MachineInstr &MI);
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/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsCodeEmitter.cpp81 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
83 void emitInstruction(MachineBasicBlock::instr_iterator MI,
101 unsigned getMachineOpValue(const MachineInstr &MI,
104 unsigned getRelocation(const MachineInstr &MI,
107 unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
108 unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
109 unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
112 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
113 unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
114 unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
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/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h32 void printInstruction(const MCInst *MI, raw_ostream &O);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
40 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum, in printAddrRegExtendOperand() argument
42 printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize); in printAddrRegExtendOperand()
46 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
50 void printAddSubImmLSL0Operand(const MCInst *MI,
52 void printAddSubImmLSL12Operand(const MCInst *MI,
55 void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
58 void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
59 void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/InstPrinter/
DHexagonInstPrinter.cpp40 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
42 printInst((const HexagonMCInst*)(MI), O, Annot); in printInst()
45 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O, in printInst() argument
50 if (MI->getOpcode() == Hexagon::ENDLOOP0) { in printInst()
52 assert(MI->isPacketEnd() && "Loop-end must also end the packet"); in printInst()
54 if (MI->isPacketStart()) { in printInst()
61 Nop.setPacketStart (MI->isPacketStart()); in printInst()
66 if (MI->isPacketEnd()) in printInst()
69 printInstruction(MI, O); in printInst()
73 if (MI->isPacketStart()) in printInst()
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/freebsd-10-stable/contrib/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
73 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
79 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
82 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
88 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp126 MachineInstr &MI = *II; in eliminateFrameIndex() local
127 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); in eliminateFrameIndex()
130 MachineFunction &MF = *MI.getParent()->getParent(); in eliminateFrameIndex()
146 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
147 !TII.isSpillPredRegOp(&MI)) { in eliminateFrameIndex()
149 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false, in eliminateFrameIndex()
151 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset); in eliminateFrameIndex()
154 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex()
163 if ( (MI.getOpcode() == Hexagon::LDriw) || in eliminateFrameIndex()
164 (MI.getOpcode() == Hexagon::LDrid) || in eliminateFrameIndex()
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DHexagonSplitTFRCondSets.cpp91 MachineInstr *MI = MII; in runOnMachineFunction() local
93 switch(MI->getOpcode()) { in runOnMachineFunction()
97 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
98 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
99 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction()
101 if (MI->getOpcode() == Hexagon::TFR_condset_rr || in runOnMachineFunction()
102 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { in runOnMachineFunction()
106 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { in runOnMachineFunction()
114 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), in runOnMachineFunction()
115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
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DHexagonVLIWPacketizer.cpp128 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
132 bool isSoloInstruction(MachineInstr *MI);
142 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
144 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
145 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
148 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
153 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
157 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
160 bool DemoteToDotOld(MachineInstr* MI);
165 bool isNewifiable(MachineInstr* MI);
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DHexagonInstrInfo.h48 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
56 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
72 virtual bool analyzeCompare(const MachineInstr *MI,
104 MachineInstr* MI,
109 MachineInstr* MI, in foldMemoryOperandImpl() argument
117 virtual bool isBranch(const MachineInstr *MI) const;
118 virtual bool isPredicable(MachineInstr *MI) const;
120 PredicateInstruction(MachineInstr *MI,
133 virtual bool isPredicated(const MachineInstr *MI) const;
135 virtual bool isPredicatedTrue(const MachineInstr *MI) const;
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DHexagonAsmPrinter.h39 virtual void EmitInstruction(const MachineInstr *MI);
43 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
44 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
47 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
55 void printInstruction(const MachineInstr *MI, raw_ostream &O);
69 void printImmOperand(const MachineInstr *MI, unsigned OpNo, in printImmOperand() argument
71 int value = MI->getOperand(OpNo).getImm(); in printImmOperand()
75 void printNegImmOperand(const MachineInstr *MI, unsigned OpNo, in printNegImmOperand() argument
77 int value = MI->getOperand(OpNo).getImm(); in printNegImmOperand()
81 void printMEMriOperand(const MachineInstr *MI, unsigned OpNo, in printMEMriOperand() argument
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/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, in splitMove() argument
52 MachineBasicBlock *MBB = MI->getParent(); in splitMove()
57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); in splitMove()
58 MBB->insert(MI, EarlierMI); in splitMove()
62 MachineOperand &LowRegOp = MI->getOperand(0); in splitMove()
69 MachineOperand &LowOffsetOp = MI->getOperand(2); in splitMove()
78 MI->setDesc(get(LowOpcode)); in splitMove()
82 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const { in splitAdjDynAlloc()
83 MachineBasicBlock *MBB = MI->getParent(); in splitAdjDynAlloc()
86 MachineOperand &OffsetMO = MI->getOperand(2); in splitAdjDynAlloc()
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/freebsd-10-stable/contrib/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp30 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
31 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
32 return MI.getOperand(OpNo).getReg() == R; in isReg()
77 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
79 switch (MI->getOpcode()) { in printInst()
89 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) in printInst()
90 printInstruction(MI, O); in printInst()
93 switch (MI->getOpcode()) { in printInst()
161 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
163 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
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/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp38 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
41 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
42 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
43 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
44 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
54 printOperand(MI, 0, O); in printInst()
56 printOperand(MI, 1, O); in printInst()
64 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
65 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
67 printOperand(MI, 0, O); in printInst()
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/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp37 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
43 uint64_t getBinaryCodeForInstr(const MCInst &MI,
48 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
55 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
57 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
59 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
61 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
63 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
70 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
74 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, in getPC16DBLEncoding() argument
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/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp48 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
50 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
52 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
54 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
56 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
58 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
60 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
62 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
64 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
66 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCCodeEmitter.cpp53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
60 unsigned getMachineOpValue(const MachineInstr &MI,
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
66 unsigned getAbsDirectBrEncoding(const MachineInstr &MI,
68 unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const;
71 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
72 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
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