Lines Matching refs:MI
75 void SkipIfDead(MachineInstr &MI);
77 void If(MachineInstr &MI);
78 void Else(MachineInstr &MI);
79 void Break(MachineInstr &MI);
80 void IfBreak(MachineInstr &MI);
81 void ElseBreak(MachineInstr &MI);
82 void Loop(MachineInstr &MI);
83 void EndCf(MachineInstr &MI);
85 void Kill(MachineInstr &MI);
86 void Branch(MachineInstr &MI);
88 void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
89 void IndirectSrc(MachineInstr &MI);
90 void IndirectDst(MachineInstr &MI);
160 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) { in SkipIfDead() argument
162 MachineBasicBlock &MBB = *MI.getParent(); in SkipIfDead()
163 DebugLoc DL = MI.getDebugLoc(); in SkipIfDead()
170 MachineBasicBlock::iterator Insert = &MI; in SkipIfDead()
194 void SILowerControlFlowPass::If(MachineInstr &MI) { in If() argument
195 MachineBasicBlock &MBB = *MI.getParent(); in If()
196 DebugLoc DL = MI.getDebugLoc(); in If()
197 unsigned Reg = MI.getOperand(0).getReg(); in If()
198 unsigned Vcc = MI.getOperand(1).getReg(); in If()
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
207 Skip(MI, MI.getOperand(2)); in If()
209 MI.eraseFromParent(); in If()
212 void SILowerControlFlowPass::Else(MachineInstr &MI) { in Else() argument
213 MachineBasicBlock &MBB = *MI.getParent(); in Else()
214 DebugLoc DL = MI.getDebugLoc(); in Else()
215 unsigned Dst = MI.getOperand(0).getReg(); in Else()
216 unsigned Src = MI.getOperand(1).getReg(); in Else()
222 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
226 Skip(MI, MI.getOperand(2)); in Else()
228 MI.eraseFromParent(); in Else()
231 void SILowerControlFlowPass::Break(MachineInstr &MI) { in Break() argument
232 MachineBasicBlock &MBB = *MI.getParent(); in Break()
233 DebugLoc DL = MI.getDebugLoc(); in Break()
235 unsigned Dst = MI.getOperand(0).getReg(); in Break()
236 unsigned Src = MI.getOperand(1).getReg(); in Break()
238 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in Break()
242 MI.eraseFromParent(); in Break()
245 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) { in IfBreak() argument
246 MachineBasicBlock &MBB = *MI.getParent(); in IfBreak()
247 DebugLoc DL = MI.getDebugLoc(); in IfBreak()
249 unsigned Dst = MI.getOperand(0).getReg(); in IfBreak()
250 unsigned Vcc = MI.getOperand(1).getReg(); in IfBreak()
251 unsigned Src = MI.getOperand(2).getReg(); in IfBreak()
253 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in IfBreak()
257 MI.eraseFromParent(); in IfBreak()
260 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) { in ElseBreak() argument
261 MachineBasicBlock &MBB = *MI.getParent(); in ElseBreak()
262 DebugLoc DL = MI.getDebugLoc(); in ElseBreak()
264 unsigned Dst = MI.getOperand(0).getReg(); in ElseBreak()
265 unsigned Saved = MI.getOperand(1).getReg(); in ElseBreak()
266 unsigned Src = MI.getOperand(2).getReg(); in ElseBreak()
268 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in ElseBreak()
272 MI.eraseFromParent(); in ElseBreak()
275 void SILowerControlFlowPass::Loop(MachineInstr &MI) { in Loop() argument
276 MachineBasicBlock &MBB = *MI.getParent(); in Loop()
277 DebugLoc DL = MI.getDebugLoc(); in Loop()
278 unsigned Src = MI.getOperand(0).getReg(); in Loop()
280 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC) in Loop()
284 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in Loop()
285 .addOperand(MI.getOperand(1)) in Loop()
288 MI.eraseFromParent(); in Loop()
291 void SILowerControlFlowPass::EndCf(MachineInstr &MI) { in EndCf() argument
292 MachineBasicBlock &MBB = *MI.getParent(); in EndCf()
293 DebugLoc DL = MI.getDebugLoc(); in EndCf()
294 unsigned Reg = MI.getOperand(0).getReg(); in EndCf()
301 MI.eraseFromParent(); in EndCf()
304 void SILowerControlFlowPass::Branch(MachineInstr &MI) { in Branch() argument
305 MachineBasicBlock *Next = MI.getParent()->getNextNode(); in Branch()
306 MachineBasicBlock *Target = MI.getOperand(0).getMBB(); in Branch()
308 MI.eraseFromParent(); in Branch()
313 void SILowerControlFlowPass::Kill(MachineInstr &MI) { in Kill() argument
315 MachineBasicBlock &MBB = *MI.getParent(); in Kill()
316 DebugLoc DL = MI.getDebugLoc(); in Kill()
325 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC) in Kill()
327 .addOperand(MI.getOperand(0)); in Kill()
329 MI.eraseFromParent(); in Kill()
332 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) { in LoadM0() argument
334 MachineBasicBlock &MBB = *MI.getParent(); in LoadM0()
335 DebugLoc DL = MI.getDebugLoc(); in LoadM0()
336 MachineBasicBlock::iterator I = MI; in LoadM0()
338 unsigned Save = MI.getOperand(1).getReg(); in LoadM0()
339 unsigned Idx = MI.getOperand(3).getReg(); in LoadM0()
342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0()
345 MI.eraseFromParent(); in LoadM0()
353 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save) in LoadM0()
357 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC) in LoadM0()
361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0()
365 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC) in LoadM0()
370 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC) in LoadM0()
377 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in LoadM0()
382 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in LoadM0()
387 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC) in LoadM0()
390 MI.eraseFromParent(); in LoadM0()
393 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) { in IndirectSrc() argument
395 MachineBasicBlock &MBB = *MI.getParent(); in IndirectSrc()
396 DebugLoc DL = MI.getDebugLoc(); in IndirectSrc()
398 unsigned Dst = MI.getOperand(0).getReg(); in IndirectSrc()
399 unsigned Vec = MI.getOperand(2).getReg(); in IndirectSrc()
400 unsigned Off = MI.getOperand(4).getImm(); in IndirectSrc()
411 LoadM0(MI, MovRel); in IndirectSrc()
414 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { in IndirectDst() argument
416 MachineBasicBlock &MBB = *MI.getParent(); in IndirectDst()
417 DebugLoc DL = MI.getDebugLoc(); in IndirectDst()
419 unsigned Dst = MI.getOperand(0).getReg(); in IndirectDst()
420 unsigned Off = MI.getOperand(4).getImm(); in IndirectDst()
421 unsigned Val = MI.getOperand(5).getReg(); in IndirectDst()
433 LoadM0(MI, MovRel); in IndirectDst()
454 MachineInstr &MI = *I; in runOnMachineFunction() local
455 if (isDS(MI.getOpcode())) { in runOnMachineFunction()
460 switch (MI.getOpcode()) { in runOnMachineFunction()
464 If(MI); in runOnMachineFunction()
468 Else(MI); in runOnMachineFunction()
472 Break(MI); in runOnMachineFunction()
476 IfBreak(MI); in runOnMachineFunction()
480 ElseBreak(MI); in runOnMachineFunction()
485 Loop(MI); in runOnMachineFunction()
490 SkipIfDead(MI); in runOnMachineFunction()
493 EndCf(MI); in runOnMachineFunction()
498 SkipIfDead(MI); in runOnMachineFunction()
501 Kill(MI); in runOnMachineFunction()
505 Branch(MI); in runOnMachineFunction()
509 IndirectSrc(MI); in runOnMachineFunction()
517 IndirectDst(MI); in runOnMachineFunction()