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Searched refs:I915_WRITE (Results 1 – 25 of 29) sorted by relevance

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/freebsd-10-stable/sys/dev/drm2/i915/
Di915_suspend.c93 I915_WRITE(reg + (i << 2), array[i]); in i915_restore_palette()
429 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); in i915_restore_modeset_reg()
431 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); in i915_restore_modeset_reg()
453 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); in i915_restore_modeset_reg()
454 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); in i915_restore_modeset_reg()
460 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & in i915_restore_modeset_reg()
465 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); in i915_restore_modeset_reg()
466 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); in i915_restore_modeset_reg()
468 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); in i915_restore_modeset_reg()
472 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD); in i915_restore_modeset_reg()
[all …]
Dintel_pm.c72 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_disable_fbc()
105 I915_WRITE(FBC_TAG + (i * 4), 0); in i8xx_enable_fbc()
110 I915_WRITE(FBC_CONTROL2, fbc_ctl2); in i8xx_enable_fbc()
111 I915_WRITE(FBC_FENCE_OFF, crtc->y); in i8xx_enable_fbc()
120 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_enable_fbc()
147 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); in g4x_enable_fbc()
149 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | in g4x_enable_fbc()
152 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); in g4x_enable_fbc()
155 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); in g4x_enable_fbc()
169 I915_WRITE(DPFC_CONTROL, dpfc_ctl); in g4x_disable_fbc()
[all …]
Di915_irq.c50 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_enable_display_irq()
60 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_disable_display_irq()
73 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); in i915_enable_pipestat()
85 I915_WRITE(reg, dev_priv->pipestat[pipe]); in i915_disable_pipestat()
383 I915_WRITE(GEN6_PMIMR, 0); in gen6_pm_rps_work_func()
401 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen6_pm_rps_work_func()
407 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen6_pm_rps_work_func()
463 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); in gen6_queue_rps_work()
508 I915_WRITE(reg, pipe_stats[pipe]); in valleyview_irq_handler()
523 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); in valleyview_irq_handler()
[all …]
Dintel_ddi.c91 I915_WRITE(reg, ddi_translations[i]); in intel_prepare_ddi_buffers()
146 I915_WRITE(SPLL_CTL, in hsw_fdi_link_train()
152 I915_WRITE(PORT_CLK_SEL(PORT_E), in hsw_fdi_link_train()
154 I915_WRITE(PIPE_CLK_SEL(pipe), in hsw_fdi_link_train()
162 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
171 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
181 I915_WRITE(reg, in hsw_fdi_link_train()
197 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
210 I915_WRITE(DDI_FUNC_CTL(pipe), in hsw_fdi_link_train()
217 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
[all …]
Dintel_sprite.c131 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); in ivb_update_plane()
132 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); in ivb_update_plane()
134 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); in ivb_update_plane()
139 I915_WRITE(SPRLINOFF(pipe), offset); in ivb_update_plane()
141 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); in ivb_update_plane()
142 I915_WRITE(SPRSCALE(pipe), sprscale); in ivb_update_plane()
143 I915_WRITE(SPRCTL(pipe), sprctl); in ivb_update_plane()
156 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); in ivb_disable_plane()
158 I915_WRITE(SPRSCALE(pipe), 0); in ivb_disable_plane()
179 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); in ivb_update_colorkey()
[all …]
Dintel_tv.c802 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_tv_dpms()
807 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_tv_dpms()
995 I915_WRITE(TV_H_CTL_1, hctl1); in intel_tv_mode_set()
996 I915_WRITE(TV_H_CTL_2, hctl2); in intel_tv_mode_set()
997 I915_WRITE(TV_H_CTL_3, hctl3); in intel_tv_mode_set()
998 I915_WRITE(TV_V_CTL_1, vctl1); in intel_tv_mode_set()
999 I915_WRITE(TV_V_CTL_2, vctl2); in intel_tv_mode_set()
1000 I915_WRITE(TV_V_CTL_3, vctl3); in intel_tv_mode_set()
1001 I915_WRITE(TV_V_CTL_4, vctl4); in intel_tv_mode_set()
1002 I915_WRITE(TV_V_CTL_5, vctl5); in intel_tv_mode_set()
[all …]
Dintel_hdmi.c142 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
145 I915_WRITE(VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
153 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
191 I915_WRITE(reg, val); in ibx_write_infoframe()
194 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
202 I915_WRITE(reg, val); in ibx_write_infoframe()
230 I915_WRITE(reg, val); in cpt_write_infoframe()
233 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
241 I915_WRITE(reg, val); in cpt_write_infoframe()
263 I915_WRITE(reg, val); in vlv_write_infoframe()
[all …]
Dintel_display.c368 I915_WRITE(DPIO_REG, reg); in intel_dpio_read()
369 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | in intel_dpio_read()
393 I915_WRITE(DPIO_DATA, val);
394 I915_WRITE(DPIO_REG, reg);
395 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
410 I915_WRITE(DPIO_CTL, 0); in vlv_init_dpio()
412 I915_WRITE(DPIO_CTL, 1); in vlv_init_dpio()
847 I915_WRITE(pipestat_reg, in intel_wait_for_vblank()
1315 I915_WRITE(reg, val); in intel_enable_pll()
1318 I915_WRITE(reg, val); in intel_enable_pll()
[all …]
Dintel_crt.c78 I915_WRITE(PCH_ADPA, temp); in pch_crt_dpms()
106 I915_WRITE(ADPA, temp); in gmch_crt_dpms()
164 I915_WRITE(dpll_md_reg, in intel_crt_mode_set()
183 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); in intel_crt_mode_set()
185 I915_WRITE(adpa_reg, adpa); in intel_crt_mode_set()
210 I915_WRITE(PCH_ADPA, adpa); in intel_ironlake_crt_detect_hotplug()
218 I915_WRITE(PCH_ADPA, save_adpa); in intel_ironlake_crt_detect_hotplug()
267 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); in intel_crt_detect_hotplug()
280 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
283 I915_WRITE(PORT_HOTPLUG_EN, orig); in intel_crt_detect_hotplug()
[all …]
Dintel_iic.c113 I915_WRITE(DSPCLK_GATE_D, val); in intel_iic_quirk_set()
144 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_iic_reset()
245 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_read()
289 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write()
290 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_write()
304 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write()
347 I915_WRITE(GMBUS5 + reg_offset, gmbus5); in gmbus_xfer_index_read()
353 I915_WRITE(GMBUS5 + reg_offset, 0); in gmbus_xfer_index_read()
378 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); in intel_gmbus_transfer()
411 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); in intel_gmbus_transfer()
[all …]
Dintel_ringbuffer.h15 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
18 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
21 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
24 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
27 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
Dintel_dp.c409 I915_WRITE(ch_data + i, in intel_dp_aux_ch()
413 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
430 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
798 I915_WRITE(TRANSDATA_M1(pipe), in intel_dp_set_m_n()
801 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); in intel_dp_set_m_n()
802 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); in intel_dp_set_m_n()
803 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); in intel_dp_set_m_n()
805 I915_WRITE(PIPE_GMCH_DATA_M(pipe), in intel_dp_set_m_n()
808 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); in intel_dp_set_m_n()
809 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); in intel_dp_set_m_n()
[all …]
Dintel_lvds.c85 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); in intel_lvds_enable()
98 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); in intel_lvds_enable()
99 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); in intel_lvds_enable()
103 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_lvds_enable()
131 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_lvds_disable()
138 I915_WRITE(PFIT_CONTROL, 0); in intel_lvds_disable()
142 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); in intel_lvds_disable()
290 I915_WRITE(BCLRPAT(pipe), 0); in intel_lvds_mode_fixup()
1080 I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); in intel_lvds_init()
1085 I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); in intel_lvds_init()
[all …]
Di915_gem_stolen.c145 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); in i915_setup_compression()
147 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); in i915_setup_compression()
149 I915_WRITE(FBC_CFB_BASE, cfb_base); in i915_setup_compression()
150 I915_WRITE(FBC_LL_BASE, ll_base); in i915_setup_compression()
Dintel_panel.c147 I915_WRITE(BLC_PWM_PCH_CTL2, in i915_read_blc_pwm_ctl()
157 I915_WRITE(BLC_PWM_CTL, in i915_read_blc_pwm_ctl()
159 I915_WRITE(BLC_PWM_CTL2, in i915_read_blc_pwm_ctl()
243 I915_WRITE(BLC_PWM_CPU_CTL, val | level); in intel_pch_panel_set_backlight()
270 I915_WRITE(BLC_PWM_CTL, tmp | level); in intel_panel_actually_set_backlight()
Dintel_ringbuffer.c429 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
431 I915_WRITE(GFX_MODE_GEN7, in init_render_ring()
449 I915_WRITE(CACHE_MODE_0, in init_render_ring()
461 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
676 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in gen5_ring_get_irq()
692 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in gen5_ring_put_irq()
709 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_get_irq()
725 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_put_irq()
790 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); in intel_ring_setup_status_page()
849 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in gen6_ring_get_irq()
[all …]
Di915_drv.c741 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); in i8xx_do_reset()
745 I915_WRITE(DEBUG_RESET_I830, in i8xx_do_reset()
752 I915_WRITE(DEBUG_RESET_I830, 0); in i8xx_do_reset()
758 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); in i8xx_do_reset()
809 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, in ironlake_do_reset()
817 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, in ironlake_do_reset()
Di915_gem.c272 I915_WRITE(MI_ARB_STATE, in i915_gem_load()
394 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
401 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
403 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
405 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
439 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); in i915_gem_init_ppgtt()
442 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); in i915_gem_init_ppgtt()
445 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | in i915_gem_init_ppgtt()
447 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in i915_gem_init_ppgtt()
449 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); in i915_gem_init_ppgtt()
[all …]
Dintel_overlay.c1378 I915_WRITE(OGAMC0, attrs->gamma0); in intel_overlay_attrs()
1379 I915_WRITE(OGAMC1, attrs->gamma1); in intel_overlay_attrs()
1380 I915_WRITE(OGAMC2, attrs->gamma2); in intel_overlay_attrs()
1381 I915_WRITE(OGAMC3, attrs->gamma3); in intel_overlay_attrs()
1382 I915_WRITE(OGAMC4, attrs->gamma4); in intel_overlay_attrs()
1383 I915_WRITE(OGAMC5, attrs->gamma5); in intel_overlay_attrs()
Dintel_bios.c773 I915_WRITE(PP_ON_DELAYS, 0x019007d0); in intel_setup_bios()
776 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); in intel_setup_bios()
Di915_dma.c89 I915_WRITE(HWS_PGA, addr); in i915_write_hws_pga()
147 I915_WRITE(HWS_PGA, 0x1ffff000); in i915_free_hws()
1104 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); in i915_set_status_page()
/freebsd-10-stable/sys/dev/drm/
Di915_suspend.c83 I915_WRITE(reg + (i << 2), array[i]); in i915_restore_palette()
380 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); in i915_restore_state()
383 I915_WRITE(HWS_PGA, dev_priv->saveHWS); in i915_restore_state()
386 I915_WRITE(DSPARB, dev_priv->saveDSPARB); in i915_restore_state()
391 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & in i915_restore_state()
395 I915_WRITE(FPA0, dev_priv->saveFPA0); in i915_restore_state()
396 I915_WRITE(FPA1, dev_priv->saveFPA1); in i915_restore_state()
398 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); in i915_restore_state()
401 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); in i915_restore_state()
405 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); in i915_restore_state()
[all …]
Di915_irq.c65 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_enable_irq()
76 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_disable_irq()
99 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); in i915_enable_pipestat()
111 I915_WRITE(reg, dev_priv->pipestat[pipe]); in i915_disable_pipestat()
223 I915_WRITE(PIPEASTAT, pipea_stats); in i915_driver_irq_handler()
228 I915_WRITE(PIPEBSTAT, pipeb_stats); in i915_driver_irq_handler()
236 I915_WRITE(IIR, iir); in i915_driver_irq_handler()
496 I915_WRITE(HWSTAM, 0xeffe); in i915_driver_irq_preinstall()
497 I915_WRITE(PIPEASTAT, 0); in i915_driver_irq_preinstall()
498 I915_WRITE(PIPEBSTAT, 0); in i915_driver_irq_preinstall()
[all …]
Di915_dma.c100 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); in i915_init_phys_hws()
123 I915_WRITE(HWS_PGA, 0x1ffff000); in i915_free_hws()
246 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); in i915_dma_resume()
248 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); in i915_dma_resume()
836 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); in i915_set_status_page()
Di915_drv.h568 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) macro
602 I915_WRITE(PRB0_TAIL, outring); \

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