142 	I915_WRITE(VIDEO_DIP_CTL, val);  in g4x_write_infoframe()
145 		I915_WRITE(VIDEO_DIP_DATA, *data);  in g4x_write_infoframe()
153 	I915_WRITE(VIDEO_DIP_CTL, val);  in g4x_write_infoframe()
191 	I915_WRITE(reg, val);  in ibx_write_infoframe()
194 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in ibx_write_infoframe()
202 	I915_WRITE(reg, val);  in ibx_write_infoframe()
230 	I915_WRITE(reg, val);  in cpt_write_infoframe()
233 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in cpt_write_infoframe()
241 	I915_WRITE(reg, val);  in cpt_write_infoframe()
263 	I915_WRITE(reg, val);  in vlv_write_infoframe()
266 		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in vlv_write_infoframe()
274 	I915_WRITE(reg, val);  in vlv_write_infoframe()
295 	I915_WRITE(ctl_reg, val);  in hsw_write_infoframe()
298 		I915_WRITE(data_reg + i, *data);  in hsw_write_infoframe()
303 	I915_WRITE(ctl_reg, val);  in hsw_write_infoframe()
388 	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);  in intel_hdmi_mode_set()
412 		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);  in intel_hdmi_dpms()
422 	I915_WRITE(intel_hdmi->sdvox_reg, temp);  in intel_hdmi_dpms()
429 		I915_WRITE(intel_hdmi->sdvox_reg, temp);  in intel_hdmi_dpms()
710 		I915_WRITE(VIDEO_DIP_CTL, 0);  in intel_hdmi_init()
714 			I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);  in intel_hdmi_init()
721 			I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);  in intel_hdmi_init()
725 			I915_WRITE(TVIDEO_DIP_CTL(i), 0);  in intel_hdmi_init()
729 			I915_WRITE(TVIDEO_DIP_CTL(i), 0);  in intel_hdmi_init()
750 		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);  in intel_hdmi_init()