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Searched refs:pipe_config (Results 1 – 23 of 23) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_hdmi.c180 const struct intel_crtc_state *pipe_config) in g4x_infoframe_enabled() argument
237 const struct intel_crtc_state *pipe_config) in ibx_infoframe_enabled() argument
241 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; in ibx_infoframe_enabled()
300 const struct intel_crtc_state *pipe_config) in cpt_infoframe_enabled() argument
303 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; in cpt_infoframe_enabled()
355 const struct intel_crtc_state *pipe_config) in vlv_infoframe_enabled() argument
359 enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; in vlv_infoframe_enabled()
412 const struct intel_crtc_state *pipe_config) in hsw_infoframe_enabled() argument
415 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframe_enabled()
952 struct intel_crtc_state *pipe_config) in intel_hdmi_get_config() argument
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HDintel_dp_mst.c34 struct intel_crtc_state *pipe_config, in intel_dp_mst_compute_config() argument
42 struct drm_atomic_state *state = pipe_config->base.state; in intel_dp_mst_compute_config()
45 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_mst_compute_config()
50 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
63 pipe_config->lane_count = lane_count; in intel_dp_mst_compute_config()
65 pipe_config->pipe_bpp = bpp; in intel_dp_mst_compute_config()
67 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); in intel_dp_mst_compute_config()
70 pipe_config->has_audio = true; in intel_dp_mst_compute_config()
73 pipe_config->pbn = mst_pbn; in intel_dp_mst_compute_config()
84 pipe_config->port_clock, in intel_dp_mst_compute_config()
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HDintel_display.c120 struct intel_crtc_state *pipe_config);
122 struct intel_crtc_state *pipe_config);
137 const struct intel_crtc_state *pipe_config);
139 const struct intel_crtc_state *pipe_config);
218 const struct intel_crtc_state *pipe_config) in intel_fdi_link_freq() argument
221 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
1403 const struct intel_crtc_state *pipe_config) in _vlv_enable_pll() argument
1408 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1421 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1431 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
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HDintel_crt.c120 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
122 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
124 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
128 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
132 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
140 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); in hsw_crt_get_config()
248 const struct intel_crtc_state *pipe_config, in hsw_pre_pll_enable_crt() argument
251 struct drm_crtc *crtc = pipe_config->base.crtc; in hsw_pre_pll_enable_crt()
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HDintel_ddi.c1277 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) in ddi_dotclock_get() argument
1281 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
1282 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1283 &pipe_config->fdi_m_n); in ddi_dotclock_get()
1284 else if (intel_crtc_has_dp_encoder(pipe_config)) in ddi_dotclock_get()
1285 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1286 &pipe_config->dp_m_n); in ddi_dotclock_get()
1287 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1288 dotclock = pipe_config->port_clock * 2 / 3; in ddi_dotclock_get()
1290 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
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HDintel_lvds.c123 struct intel_crtc_state *pipe_config) in intel_lvds_get_config() argument
139 pipe_config->base.adjusted_mode.flags |= flags; in intel_lvds_get_config()
142 pipe_config->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
149 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
152 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
233 const struct intel_crtc_state *pipe_config, in intel_pre_enable_lvds() argument
238 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_pre_enable_lvds()
239 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pre_enable_lvds()
246 pipe_config->shared_dpll); in intel_pre_enable_lvds()
269 temp |= pipe_config->gmch_pfit.lvds_border_bits; in intel_pre_enable_lvds()
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HDintel_dvo.c156 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
172 pipe_config->base.adjusted_mode.flags |= flags; in intel_dvo_get_config()
174 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
192 const struct intel_crtc_state *pipe_config, in intel_enable_dvo() argument
201 &pipe_config->base.mode, in intel_enable_dvo()
202 &pipe_config->base.adjusted_mode); in intel_enable_dvo()
241 struct intel_crtc_state *pipe_config, in intel_dvo_compute_config() argument
247 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dvo_compute_config()
261 const struct intel_crtc_state *pipe_config, in intel_dvo_pre_enable() argument
265 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dvo_pre_enable()
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HDintel_panel.c105 struct intel_crtc_state *pipe_config, in intel_pch_panel_fitting() argument
108 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pch_panel_fitting()
112 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && in intel_pch_panel_fitting()
113 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && in intel_pch_panel_fitting()
114 !pipe_config->ycbcr420) in intel_pch_panel_fitting()
119 width = pipe_config->pipe_src_w; in intel_pch_panel_fitting()
120 height = pipe_config->pipe_src_h; in intel_pch_panel_fitting()
129 * pipe_config->pipe_src_h; in intel_pch_panel_fitting()
130 u32 scaled_height = pipe_config->pipe_src_w in intel_pch_panel_fitting()
133 width = scaled_height / pipe_config->pipe_src_h; in intel_pch_panel_fitting()
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HDintel_dp.c1483 struct intel_crtc_state *pipe_config) in intel_dp_set_clock() argument
1506 if (pipe_config->port_clock == divisor[i].clock) { in intel_dp_set_clock()
1507 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
1508 pipe_config->clock_set = true; in intel_dp_set_clock()
1589 struct intel_crtc_state *pipe_config) in intel_dp_compute_bpp() argument
1593 bpp = pipe_config->pipe_bpp; in intel_dp_compute_bpp()
1601 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; in intel_dp_compute_bpp()
1602 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3; in intel_dp_compute_bpp()
1604 pipe_config->pipe_bpp); in intel_dp_compute_bpp()
1628 struct intel_crtc_state *pipe_config, in intel_dp_compute_config() argument
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HDintel_dsi.c304 struct intel_crtc_state *pipe_config, in intel_dsi_compute_config() argument
311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dsi_compute_config()
313 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dsi_compute_config()
322 intel_gmch_panel_fitting(crtc, pipe_config, in intel_dsi_compute_config()
325 intel_pch_panel_fitting(crtc, pipe_config, in intel_dsi_compute_config()
339 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
341 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
344 ret = intel_compute_dsi_pll(encoder, pipe_config); in intel_dsi_compute_config()
348 pipe_config->clock_set = true; in intel_dsi_compute_config()
738 const struct intel_crtc_state *pipe_config);
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HDintel_sdvo.c998 const struct intel_crtc_state *pipe_config) in intel_sdvo_set_avi_infoframe() argument
1006 &pipe_config->base.adjusted_mode, in intel_sdvo_set_avi_infoframe()
1014 if (pipe_config->limited_color_range) in intel_sdvo_set_avi_infoframe()
1093 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1095 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1096 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1116 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1120 struct intel_crtc_state *pipe_config, in intel_sdvo_compute_config() argument
1126 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_sdvo_compute_config()
1127 struct drm_display_mode *mode = &pipe_config->base.mode; in intel_sdvo_compute_config()
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HDintel_tv.c817 const struct intel_crtc_state *pipe_config, in intel_enable_tv() argument
869 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
871 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_tv_get_config()
876 struct intel_crtc_state *pipe_config, in intel_tv_compute_config() argument
884 pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock; in intel_tv_compute_config()
886 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
889 pipe_config->base.adjusted_mode.flags = 0; in intel_tv_compute_config()
979 const struct intel_crtc_state *pipe_config, in intel_tv_pre_enable() argument
HDintel_drv.h249 struct intel_crtc_state *pipe_config);
1071 const struct intel_crtc_state *pipe_config);
1290 struct intel_crtc_state *pipe_config);
1293 struct intel_crtc_state *pipe_config);
1472 struct intel_crtc_state *pipe_config);
1484 struct intel_crtc_state *pipe_config);
1526 struct intel_crtc_state *pipe_config,
1671 struct intel_crtc_state *pipe_config,
1716 struct intel_crtc_state *pipe_config,
1719 struct intel_crtc_state *pipe_config,
HDintel_overlay.c967 const struct intel_crtc_state *pipe_config = in check_overlay_dst() local
970 if (rec->dst_x < pipe_config->pipe_src_w && in check_overlay_dst()
971 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && in check_overlay_dst()
972 rec->dst_y < pipe_config->pipe_src_h && in check_overlay_dst()
973 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) in check_overlay_dst()
HDi915_drv.h724 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
/dragonfly/sys/dev/drm/amd/display/dc/core/
HDdc_debug.c162 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
251 update->plane_info->tiling_info.gfx8.pipe_config, in update_surface_trace()
/dragonfly/sys/dev/drm/amd/display/dc/
HDdc_hw_types.h347 unsigned int pipe_config; member
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_mem_input.c380 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_mem_input_v.c191 set_reg_field_value(value, info->gfx8.pipe_config, in program_tiling()
/dragonfly/sys/dev/drm/radeon/
HDatombios_crtc.c1349 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base() local
1351 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); in dce4_crtc_do_set_base()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c1834 u32 pipe_config; in dce_v10_0_crtc_do_set_base() local
1872 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1977 pipe_config); in dce_v10_0_crtc_do_set_base()
HDdce_v11_0.c1876 u32 pipe_config; in dce_v11_0_crtc_do_set_base() local
1914 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2019 pipe_config); in dce_v11_0_crtc_do_set_base()
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
HDamdgpu_dm.c2106 plane_state->tiling_info.gfx8.pipe_config = in fill_plane_attributes_from_fb()