Lines Matching refs:pipe_config
120 struct intel_crtc_state *pipe_config);
122 struct intel_crtc_state *pipe_config);
137 const struct intel_crtc_state *pipe_config);
139 const struct intel_crtc_state *pipe_config);
218 const struct intel_crtc_state *pipe_config) in intel_fdi_link_freq() argument
221 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
1403 const struct intel_crtc_state *pipe_config) in _vlv_enable_pll() argument
1408 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1421 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1431 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1432 _vlv_enable_pll(crtc, pipe_config); in vlv_enable_pll()
1434 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1440 const struct intel_crtc_state *pipe_config) in _chv_enable_pll() argument
1462 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1472 const struct intel_crtc_state *pipe_config) in chv_enable_pll() argument
1482 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1483 _chv_enable_pll(crtc, pipe_config); in chv_enable_pll()
1493 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1495 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1503 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
4999 struct intel_crtc_state *pipe_config = in intel_post_plane_update() local
5006 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); in intel_post_plane_update()
5008 if (pipe_config->update_wm_post && pipe_config->base.active) in intel_post_plane_update()
5021 (needs_modeset(&pipe_config->base) || in intel_post_plane_update()
5028 struct intel_crtc_state *pipe_config) in intel_pre_plane_update() argument
5037 bool modeset = needs_modeset(&pipe_config->base); in intel_pre_plane_update()
5048 intel_fbc_pre_update(crtc, pipe_config, primary_state); in intel_pre_plane_update()
5065 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) in intel_pre_plane_update()
5075 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) in intel_pre_plane_update()
5082 if (needs_modeset(&pipe_config->base)) in intel_pre_plane_update()
5101 pipe_config); in intel_pre_plane_update()
5102 else if (pipe_config->update_wm_pre) in intel_pre_plane_update()
5246 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, in ironlake_crtc_enable() argument
5249 struct drm_crtc *crtc = pipe_config->base.crtc; in ironlake_crtc_enable()
5293 intel_encoders_pre_enable(crtc, pipe_config, old_state); in ironlake_crtc_enable()
5311 intel_color_load_luts(&pipe_config->base); in ironlake_crtc_enable()
5318 ironlake_pch_enable(pipe_config); in ironlake_crtc_enable()
5323 intel_encoders_enable(crtc, pipe_config, old_state); in ironlake_crtc_enable()
5355 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, in haswell_crtc_enable() argument
5358 struct drm_crtc *crtc = pipe_config->base.crtc; in haswell_crtc_enable()
5370 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); in haswell_crtc_enable()
5399 intel_color_set_csc(&pipe_config->base); in haswell_crtc_enable()
5403 intel_encoders_pre_enable(crtc, pipe_config, old_state); in haswell_crtc_enable()
5406 intel_ddi_enable_pipe_clock(pipe_config); in haswell_crtc_enable()
5423 intel_color_load_luts(&pipe_config->base); in haswell_crtc_enable()
5425 intel_ddi_set_pipe_settings(pipe_config); in haswell_crtc_enable()
5427 intel_ddi_enable_transcoder_func(pipe_config); in haswell_crtc_enable()
5430 dev_priv->display.initial_watermarks(old_intel_state, pipe_config); in haswell_crtc_enable()
5437 lpt_pch_enable(pipe_config); in haswell_crtc_enable()
5440 intel_ddi_set_vc_payload_alloc(pipe_config, true); in haswell_crtc_enable()
5445 intel_encoders_enable(crtc, pipe_config, old_state); in haswell_crtc_enable()
5454 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; in haswell_crtc_enable()
5575 struct intel_crtc_state *pipe_config = crtc->config; in i9xx_pfit_enable() local
5577 if (!pipe_config->gmch_pfit.control) in i9xx_pfit_enable()
5587 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); in i9xx_pfit_enable()
5588 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); in i9xx_pfit_enable()
5679 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, in valleyview_crtc_enable() argument
5684 struct drm_crtc *crtc = pipe_config->base.crtc; in valleyview_crtc_enable()
5712 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); in valleyview_crtc_enable()
5722 intel_encoders_pre_enable(crtc, pipe_config, old_state); in valleyview_crtc_enable()
5726 intel_color_load_luts(&pipe_config->base); in valleyview_crtc_enable()
5729 pipe_config); in valleyview_crtc_enable()
5735 intel_encoders_enable(crtc, pipe_config, old_state); in valleyview_crtc_enable()
5747 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, in i9xx_crtc_enable() argument
5752 struct drm_crtc *crtc = pipe_config->base.crtc; in i9xx_crtc_enable()
5776 intel_encoders_pre_enable(crtc, pipe_config, old_state); in i9xx_crtc_enable()
5778 i9xx_enable_pll(intel_crtc, pipe_config); in i9xx_crtc_enable()
5782 intel_color_load_luts(&pipe_config->base); in i9xx_crtc_enable()
5794 intel_encoders_enable(crtc, pipe_config, old_state); in i9xx_crtc_enable()
6065 struct intel_crtc_state *pipe_config) in ironlake_check_fdi_lanes() argument
6068 struct drm_atomic_state *state = pipe_config->base.state; in ironlake_check_fdi_lanes()
6073 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6074 if (pipe_config->fdi_lanes > 4) { in ironlake_check_fdi_lanes()
6076 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6081 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
6083 pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6098 if (pipe_config->fdi_lanes <= 2) in ironlake_check_fdi_lanes()
6109 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6114 if (pipe_config->fdi_lanes > 2) { in ironlake_check_fdi_lanes()
6116 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
6138 struct intel_crtc_state *pipe_config) in ironlake_fdi_compute_config() argument
6141 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in ironlake_fdi_compute_config()
6153 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); in ironlake_fdi_compute_config()
6158 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6160 pipe_config->fdi_lanes = lane; in ironlake_fdi_compute_config()
6162 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
6163 link_bw, &pipe_config->fdi_m_n, false); in ironlake_fdi_compute_config()
6165 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
6166 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
6167 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
6169 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6171 pipe_config->bw_constrained = true; in ironlake_fdi_compute_config()
6183 struct intel_crtc_state *pipe_config) in pipe_config_supports_ips() argument
6185 if (pipe_config->ips_force_disable) in pipe_config_supports_ips()
6188 if (pipe_config->pipe_bpp > 24) in pipe_config_supports_ips()
6202 return pipe_config->pixel_rate <= in pipe_config_supports_ips()
6207 struct intel_crtc_state *pipe_config) in hsw_compute_ips_config() argument
6212 pipe_config->ips_enabled = i915_modparams.enable_ips && in hsw_compute_ips_config()
6214 pipe_config_supports_ips(dev_priv, pipe_config); in hsw_compute_ips_config()
6226 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) in ilk_pipe_pixel_rate() argument
6230 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; in ilk_pipe_pixel_rate()
6237 if (pipe_config->pch_pfit.enabled) { in ilk_pipe_pixel_rate()
6239 uint32_t pfit_size = pipe_config->pch_pfit.size; in ilk_pipe_pixel_rate()
6241 pipe_w = pipe_config->pipe_src_w; in ilk_pipe_pixel_rate()
6242 pipe_h = pipe_config->pipe_src_h; in ilk_pipe_pixel_rate()
6275 struct intel_crtc_state *pipe_config) in intel_crtc_compute_config() argument
6279 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_crtc_compute_config()
6292 pipe_config->double_wide = true; in intel_crtc_compute_config()
6299 yesno(pipe_config->double_wide)); in intel_crtc_compute_config()
6303 if (pipe_config->ycbcr420 && pipe_config->base.ctm) { in intel_crtc_compute_config()
6319 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && in intel_crtc_compute_config()
6320 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) in intel_crtc_compute_config()
6321 pipe_config->pipe_src_w &= ~1; in intel_crtc_compute_config()
6330 intel_crtc_compute_pixel_rate(pipe_config); in intel_crtc_compute_config()
6333 hsw_compute_ips_config(crtc, pipe_config); in intel_crtc_compute_config()
6335 if (pipe_config->has_pch_encoder) in intel_crtc_compute_config()
6336 return ironlake_fdi_compute_config(crtc, pipe_config); in intel_crtc_compute_config()
6537 struct intel_crtc_state *pipe_config) in vlv_compute_dpll() argument
6539 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
6542 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
6545 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) in vlv_compute_dpll()
6546 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
6549 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
6550 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in vlv_compute_dpll()
6554 struct intel_crtc_state *pipe_config) in chv_compute_dpll() argument
6556 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
6559 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
6562 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) in chv_compute_dpll()
6563 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
6565 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
6566 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
6570 const struct intel_crtc_state *pipe_config) in vlv_prepare_pll() argument
6581 pipe_config->dpll_hw_state.dpll & in vlv_prepare_pll()
6585 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
6590 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
6591 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
6592 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
6593 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
6594 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
6631 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
6640 if (intel_crtc_has_dp_encoder(pipe_config)) { in vlv_prepare_pll()
6669 const struct intel_crtc_state *pipe_config) in chv_prepare_pll() argument
6682 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
6685 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
6688 bestn = pipe_config->dpll.n; in chv_prepare_pll()
6689 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
6690 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
6691 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
6692 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
6693 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
6694 vco = pipe_config->dpll.vco; in chv_prepare_pll()
6787 struct intel_crtc_state *pipe_config; in vlv_force_pll_on() local
6789 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); in vlv_force_pll_on()
6790 if (!pipe_config) in vlv_force_pll_on()
6793 pipe_config->base.crtc = &crtc->base; in vlv_force_pll_on()
6794 pipe_config->pixel_multiplier = 1; in vlv_force_pll_on()
6795 pipe_config->dpll = *dpll; in vlv_force_pll_on()
6798 chv_compute_dpll(crtc, pipe_config); in vlv_force_pll_on()
6799 chv_prepare_pll(crtc, pipe_config); in vlv_force_pll_on()
6800 chv_enable_pll(crtc, pipe_config); in vlv_force_pll_on()
6802 vlv_compute_dpll(crtc, pipe_config); in vlv_force_pll_on()
6803 vlv_prepare_pll(crtc, pipe_config); in vlv_force_pll_on()
6804 vlv_enable_pll(crtc, pipe_config); in vlv_force_pll_on()
6807 kfree(pipe_config); in vlv_force_pll_on()
7015 struct intel_crtc_state *pipe_config) in intel_get_pipe_timings() argument
7019 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_get_pipe_timings()
7023 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7024 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7026 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7027 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7029 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7030 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7033 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7034 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7036 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7037 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7039 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
7040 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
7043 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_pipe_timings()
7044 pipe_config->base.adjusted_mode.crtc_vtotal += 1; in intel_get_pipe_timings()
7045 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; in intel_get_pipe_timings()
7050 struct intel_crtc_state *pipe_config) in intel_get_pipe_src_size() argument
7057 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; in intel_get_pipe_src_size()
7058 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_src_size()
7060 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; in intel_get_pipe_src_size()
7061 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; in intel_get_pipe_src_size()
7065 struct intel_crtc_state *pipe_config) in intel_mode_from_pipe_config() argument
7067 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config()
7068 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; in intel_mode_from_pipe_config()
7069 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; in intel_mode_from_pipe_config()
7070 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; in intel_mode_from_pipe_config()
7072 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; in intel_mode_from_pipe_config()
7073 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; in intel_mode_from_pipe_config()
7074 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; in intel_mode_from_pipe_config()
7075 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; in intel_mode_from_pipe_config()
7077 mode->flags = pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
7080 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; in intel_mode_from_pipe_config()
7332 struct intel_crtc_state *pipe_config) in i9xx_get_pfit_config() argument
7354 pipe_config->gmch_pfit.control = tmp; in i9xx_get_pfit_config()
7355 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
7359 struct intel_crtc_state *pipe_config) in vlv_crtc_clock_get() argument
7363 int pipe = pipe_config->cpu_transcoder; in vlv_crtc_clock_get()
7369 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
7382 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
7454 struct intel_crtc_state *pipe_config) in chv_crtc_clock_get() argument
7458 int pipe = pipe_config->cpu_transcoder; in chv_crtc_clock_get()
7465 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
7484 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
7488 struct intel_crtc_state *pipe_config) in i9xx_get_pipe_config() argument
7499 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
7500 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
7512 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
7515 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
7518 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
7527 pipe_config->limited_color_range = true; in i9xx_get_pipe_config()
7530 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; in i9xx_get_pipe_config()
7532 intel_get_pipe_timings(crtc, pipe_config); in i9xx_get_pipe_config()
7533 intel_get_pipe_src_size(crtc, pipe_config); in i9xx_get_pipe_config()
7535 i9xx_get_pfit_config(crtc, pipe_config); in i9xx_get_pipe_config()
7543 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
7546 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
7550 pipe_config->pixel_multiplier = in i9xx_get_pipe_config()
7557 pipe_config->pixel_multiplier = 1; in i9xx_get_pipe_config()
7559 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7567 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
7569 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7570 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7573 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
7579 chv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7581 vlv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7583 i9xx_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7590 pipe_config->base.adjusted_mode.crtc_clock = in i9xx_get_pipe_config()
7591 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
8362 struct intel_crtc_state *pipe_config) in intel_dp_get_m_n() argument
8364 if (pipe_config->has_pch_encoder) in intel_dp_get_m_n()
8365 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); in intel_dp_get_m_n()
8367 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in intel_dp_get_m_n()
8368 &pipe_config->dp_m_n, in intel_dp_get_m_n()
8369 &pipe_config->dp_m2_n2); in intel_dp_get_m_n()
8373 struct intel_crtc_state *pipe_config) in ironlake_get_fdi_m_n_config() argument
8375 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in ironlake_get_fdi_m_n_config()
8376 &pipe_config->fdi_m_n, NULL); in ironlake_get_fdi_m_n_config()
8380 struct intel_crtc_state *pipe_config) in skylake_get_pfit_config() argument
8384 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; in skylake_get_pfit_config()
8394 pipe_config->pch_pfit.enabled = true; in skylake_get_pfit_config()
8395 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
8396 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
8498 struct intel_crtc_state *pipe_config) in ironlake_get_pfit_config() argument
8507 pipe_config->pch_pfit.enabled = true; in ironlake_get_pfit_config()
8508 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
8509 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
8590 struct intel_crtc_state *pipe_config) in ironlake_get_pipe_config() argument
8602 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
8603 pipe_config->shared_dpll = NULL; in ironlake_get_pipe_config()
8612 pipe_config->pipe_bpp = 18; in ironlake_get_pipe_config()
8615 pipe_config->pipe_bpp = 24; in ironlake_get_pipe_config()
8618 pipe_config->pipe_bpp = 30; in ironlake_get_pipe_config()
8621 pipe_config->pipe_bpp = 36; in ironlake_get_pipe_config()
8628 pipe_config->limited_color_range = true; in ironlake_get_pipe_config()
8634 pipe_config->has_pch_encoder = true; in ironlake_get_pipe_config()
8637 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in ironlake_get_pipe_config()
8640 ironlake_get_fdi_m_n_config(crtc, pipe_config); in ironlake_get_pipe_config()
8656 pipe_config->shared_dpll = in ironlake_get_pipe_config()
8658 pll = pipe_config->shared_dpll; in ironlake_get_pipe_config()
8661 &pipe_config->dpll_hw_state)); in ironlake_get_pipe_config()
8663 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
8664 pipe_config->pixel_multiplier = in ironlake_get_pipe_config()
8668 ironlake_pch_clock_get(crtc, pipe_config); in ironlake_get_pipe_config()
8670 pipe_config->pixel_multiplier = 1; in ironlake_get_pipe_config()
8673 intel_get_pipe_timings(crtc, pipe_config); in ironlake_get_pipe_config()
8674 intel_get_pipe_src_size(crtc, pipe_config); in ironlake_get_pipe_config()
8676 ironlake_get_pfit_config(crtc, pipe_config); in ironlake_get_pipe_config()
8923 struct intel_crtc_state *pipe_config) in cannonlake_get_ddi_pll() argument
8934 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in cannonlake_get_ddi_pll()
8939 struct intel_crtc_state *pipe_config) in bxt_get_ddi_pll() argument
8958 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in bxt_get_ddi_pll()
8963 struct intel_crtc_state *pipe_config) in skylake_get_ddi_pll() argument
8974 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in skylake_get_ddi_pll()
8979 struct intel_crtc_state *pipe_config) in haswell_get_ddi_pll() argument
9010 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); in haswell_get_ddi_pll()
9014 struct intel_crtc_state *pipe_config, in hsw_get_transcoder_state() argument
9026 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in hsw_get_transcoder_state()
9051 pipe_config->cpu_transcoder = TRANSCODER_EDP; in hsw_get_transcoder_state()
9054 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); in hsw_get_transcoder_state()
9059 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
9065 struct intel_crtc_state *pipe_config, in bxt_get_dsi_transcoder_state() argument
9105 pipe_config->cpu_transcoder = cpu_transcoder; in bxt_get_dsi_transcoder_state()
9109 return transcoder_is_dsi(pipe_config->cpu_transcoder); in bxt_get_dsi_transcoder_state()
9113 struct intel_crtc_state *pipe_config) in haswell_get_ddi_port_state() argument
9120 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in haswell_get_ddi_port_state()
9125 cannonlake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9127 skylake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9129 bxt_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9131 haswell_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
9133 pll = pipe_config->shared_dpll; in haswell_get_ddi_port_state()
9136 &pipe_config->dpll_hw_state)); in haswell_get_ddi_port_state()
9146 pipe_config->has_pch_encoder = true; in haswell_get_ddi_port_state()
9149 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in haswell_get_ddi_port_state()
9152 ironlake_get_fdi_m_n_config(crtc, pipe_config); in haswell_get_ddi_port_state()
9157 struct intel_crtc_state *pipe_config) in haswell_get_pipe_config() argument
9164 intel_crtc_init_scalers(crtc, pipe_config); in haswell_get_pipe_config()
9171 pipe_config->shared_dpll = NULL; in haswell_get_pipe_config()
9173 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); in haswell_get_pipe_config()
9176 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { in haswell_get_pipe_config()
9184 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { in haswell_get_pipe_config()
9185 haswell_get_ddi_port_state(crtc, pipe_config); in haswell_get_pipe_config()
9186 intel_get_pipe_timings(crtc, pipe_config); in haswell_get_pipe_config()
9189 intel_get_pipe_src_size(crtc, pipe_config); in haswell_get_pipe_config()
9191 pipe_config->gamma_mode = in haswell_get_pipe_config()
9202 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; in haswell_get_pipe_config()
9203 if (pipe_config->ycbcr420 != clrspace_yuv || in haswell_get_pipe_config()
9204 pipe_config->ycbcr420 != blend_mode_420) in haswell_get_pipe_config()
9215 skylake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9217 ironlake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
9221 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && in haswell_get_pipe_config()
9224 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && in haswell_get_pipe_config()
9225 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { in haswell_get_pipe_config()
9226 pipe_config->pixel_multiplier = in haswell_get_pipe_config()
9227 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in haswell_get_pipe_config()
9229 pipe_config->pixel_multiplier = 1; in haswell_get_pipe_config()
10025 const struct intel_crtc_state *pipe_config) in i9xx_pll_refclk() argument
10028 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
10042 struct intel_crtc_state *pipe_config) in i9xx_crtc_clock_get() argument
10046 int pipe = pipe_config->cpu_transcoder; in i9xx_crtc_clock_get()
10047 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
10051 int refclk = i9xx_pll_refclk(dev, pipe_config); in i9xx_crtc_clock_get()
10054 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get()
10056 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
10127 pipe_config->port_clock = port_clock; in i9xx_crtc_clock_get()
10150 struct intel_crtc_state *pipe_config) in ironlake_pch_clock_get() argument
10155 i9xx_crtc_clock_get(crtc, pipe_config); in ironlake_pch_clock_get()
10162 pipe_config->base.adjusted_mode.crtc_clock = in ironlake_pch_clock_get()
10163 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), in ironlake_pch_clock_get()
10164 &pipe_config->fdi_m_n); in ironlake_pch_clock_get()
10266 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); in intel_plane_atomic_calc_changes() local
10312 pipe_config->fb_changed = true; in intel_plane_atomic_calc_changes()
10329 pipe_config->update_wm_pre = true; in intel_plane_atomic_calc_changes()
10333 pipe_config->disable_cxsr = true; in intel_plane_atomic_calc_changes()
10336 pipe_config->update_wm_post = true; in intel_plane_atomic_calc_changes()
10340 pipe_config->disable_cxsr = true; in intel_plane_atomic_calc_changes()
10344 pipe_config->update_wm_pre = true; in intel_plane_atomic_calc_changes()
10345 pipe_config->update_wm_post = true; in intel_plane_atomic_calc_changes()
10350 pipe_config->fb_bits |= plane->frontbuffer_bit; in intel_plane_atomic_calc_changes()
10361 pipe_config->disable_lp_wm = true; in intel_plane_atomic_calc_changes()
10402 struct intel_crtc_state *pipe_config = in intel_crtc_atomic_check() local
10409 pipe_config->update_wm_post = true; in intel_crtc_atomic_check()
10413 !WARN_ON(pipe_config->shared_dpll)) { in intel_crtc_atomic_check()
10415 pipe_config); in intel_crtc_atomic_check()
10434 ret = dev_priv->display.compute_pipe_wm(pipe_config); in intel_crtc_atomic_check()
10453 pipe_config); in intel_crtc_atomic_check()
10460 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; in intel_crtc_atomic_check()
10465 ret = skl_update_scaler_crtc(pipe_config); in intel_crtc_atomic_check()
10469 pipe_config); in intel_crtc_atomic_check()
10472 pipe_config); in intel_crtc_atomic_check()
10511 struct intel_crtc_state *pipe_config) in connected_sink_compute_bpp() argument
10514 int bpp = pipe_config->pipe_bpp; in connected_sink_compute_bpp()
10524 pipe_config->pipe_bpp = info->bpc * 3; in connected_sink_compute_bpp()
10531 pipe_config->pipe_bpp = 24; in connected_sink_compute_bpp()
10537 struct intel_crtc_state *pipe_config) in compute_baseline_pipe_bpp() argument
10554 pipe_config->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
10556 state = pipe_config->base.state; in compute_baseline_pipe_bpp()
10564 pipe_config); in compute_baseline_pipe_bpp()
10582 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, in intel_dump_m_n_config() argument
10638 struct intel_crtc_state *pipe_config, in intel_dump_pipe_config() argument
10652 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); in intel_dump_pipe_config()
10654 buf, pipe_config->output_types); in intel_dump_pipe_config()
10657 transcoder_name(pipe_config->cpu_transcoder), in intel_dump_pipe_config()
10658 pipe_config->pipe_bpp, pipe_config->dither); in intel_dump_pipe_config()
10660 if (pipe_config->has_pch_encoder) in intel_dump_pipe_config()
10661 intel_dump_m_n_config(pipe_config, "fdi", in intel_dump_pipe_config()
10662 pipe_config->fdi_lanes, in intel_dump_pipe_config()
10663 &pipe_config->fdi_m_n); in intel_dump_pipe_config()
10665 if (pipe_config->ycbcr420) in intel_dump_pipe_config()
10668 if (intel_crtc_has_dp_encoder(pipe_config)) { in intel_dump_pipe_config()
10669 intel_dump_m_n_config(pipe_config, "dp m_n", in intel_dump_pipe_config()
10670 pipe_config->lane_count, &pipe_config->dp_m_n); in intel_dump_pipe_config()
10671 if (pipe_config->has_drrs) in intel_dump_pipe_config()
10672 intel_dump_m_n_config(pipe_config, "dp m2_n2", in intel_dump_pipe_config()
10673 pipe_config->lane_count, in intel_dump_pipe_config()
10674 &pipe_config->dp_m2_n2); in intel_dump_pipe_config()
10678 pipe_config->has_audio, pipe_config->has_infoframe); in intel_dump_pipe_config()
10681 drm_mode_debug_printmodeline(&pipe_config->base.mode); in intel_dump_pipe_config()
10683 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
10684 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
10686 pipe_config->port_clock, in intel_dump_pipe_config()
10687 pipe_config->pipe_src_w, pipe_config->pipe_src_h, in intel_dump_pipe_config()
10688 pipe_config->pixel_rate); in intel_dump_pipe_config()
10693 pipe_config->scaler_state.scaler_users, in intel_dump_pipe_config()
10694 pipe_config->scaler_state.scaler_id); in intel_dump_pipe_config()
10698 pipe_config->gmch_pfit.control, in intel_dump_pipe_config()
10699 pipe_config->gmch_pfit.pgm_ratios, in intel_dump_pipe_config()
10700 pipe_config->gmch_pfit.lvds_border_bits); in intel_dump_pipe_config()
10703 pipe_config->pch_pfit.pos, in intel_dump_pipe_config()
10704 pipe_config->pch_pfit.size, in intel_dump_pipe_config()
10705 enableddisabled(pipe_config->pch_pfit.enabled)); in intel_dump_pipe_config()
10708 pipe_config->ips_enabled, pipe_config->double_wide); in intel_dump_pipe_config()
10710 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); in intel_dump_pipe_config()
10848 struct intel_crtc_state *pipe_config) in intel_modeset_pipe_config() argument
10850 struct drm_atomic_state *state = pipe_config->base.state; in intel_modeset_pipe_config()
10858 clear_intel_crtc_state(pipe_config); in intel_modeset_pipe_config()
10860 pipe_config->cpu_transcoder = in intel_modeset_pipe_config()
10868 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
10870 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
10872 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
10874 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
10877 pipe_config); in intel_modeset_pipe_config()
10889 drm_mode_get_hv_timing(&pipe_config->base.mode, in intel_modeset_pipe_config()
10890 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
10891 &pipe_config->pipe_src_h); in intel_modeset_pipe_config()
10908 pipe_config->output_types |= 1 << encoder->type; in intel_modeset_pipe_config()
10913 pipe_config->port_clock = 0; in intel_modeset_pipe_config()
10914 pipe_config->pixel_multiplier = 1; in intel_modeset_pipe_config()
10917 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, in intel_modeset_pipe_config()
10930 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { in intel_modeset_pipe_config()
10938 if (!pipe_config->port_clock) in intel_modeset_pipe_config()
10939 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
10940 * pipe_config->pixel_multiplier; in intel_modeset_pipe_config()
10942 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); in intel_modeset_pipe_config()
10963 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
10964 !pipe_config->dither_force_disable; in intel_modeset_pipe_config()
10966 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); in intel_modeset_pipe_config()
11093 struct intel_crtc_state *pipe_config, in intel_pipe_config_compare() argument
11099 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11103 pipe_config->name); \ in intel_pipe_config_compare()
11108 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11112 pipe_config->name); \ in intel_pipe_config_compare()
11117 if (current_config->name != pipe_config->name) { \ in intel_pipe_config_compare()
11121 pipe_config->name); \ in intel_pipe_config_compare()
11127 &pipe_config->name,\ in intel_pipe_config_compare()
11137 pipe_config->name.tu, \ in intel_pipe_config_compare()
11138 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
11139 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
11140 pipe_config->name.link_m, \ in intel_pipe_config_compare()
11141 pipe_config->name.link_n); \ in intel_pipe_config_compare()
11152 &pipe_config->name, adjust) && \ in intel_pipe_config_compare()
11154 &pipe_config->name, adjust)) { \ in intel_pipe_config_compare()
11169 pipe_config->name.tu, \ in intel_pipe_config_compare()
11170 pipe_config->name.gmch_m, \ in intel_pipe_config_compare()
11171 pipe_config->name.gmch_n, \ in intel_pipe_config_compare()
11172 pipe_config->name.link_m, \ in intel_pipe_config_compare()
11173 pipe_config->name.link_n); \ in intel_pipe_config_compare()
11178 if ((current_config->name ^ pipe_config->name) & (mask)) { \ in intel_pipe_config_compare()
11183 pipe_config->name & (mask)); \ in intel_pipe_config_compare()
11188 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ in intel_pipe_config_compare()
11192 pipe_config->name); \ in intel_pipe_config_compare()
11197 ((current_config->quirks | pipe_config->quirks) & (quirk)) in intel_pipe_config_compare()
11328 const struct intel_crtc_state *pipe_config) in intel_pipe_config_sanity_check() argument
11330 if (pipe_config->has_pch_encoder) { in intel_pipe_config_sanity_check()
11331 … int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), in intel_pipe_config_sanity_check()
11332 &pipe_config->fdi_m_n); in intel_pipe_config_sanity_check()
11333 int dotclock = pipe_config->base.adjusted_mode.crtc_clock; in intel_pipe_config_sanity_check()
11546 struct intel_crtc_state *pipe_config, *sw_config; in verify_crtc_state() local
11552 pipe_config = to_intel_crtc_state(old_crtc_state); in verify_crtc_state()
11553 memset(pipe_config, 0, sizeof(*pipe_config)); in verify_crtc_state()
11554 pipe_config->base.crtc = crtc; in verify_crtc_state()
11555 pipe_config->base.state = old_state; in verify_crtc_state()
11559 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); in verify_crtc_state()
11586 pipe_config->output_types |= 1 << encoder->type; in verify_crtc_state()
11587 encoder->get_config(encoder, pipe_config); in verify_crtc_state()
11591 intel_crtc_compute_pixel_rate(pipe_config); in verify_crtc_state()
11596 intel_pipe_config_sanity_check(dev_priv, pipe_config); in verify_crtc_state()
11600 pipe_config, false)) { in verify_crtc_state()
11602 intel_dump_pipe_config(intel_crtc, pipe_config, in verify_crtc_state()
11838 struct intel_crtc_state *pipe_config; in haswell_mode_set_planes_workaround() local
11840 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); in haswell_mode_set_planes_workaround()
11841 if (IS_ERR(pipe_config)) in haswell_mode_set_planes_workaround()
11842 return PTR_ERR(pipe_config); in haswell_mode_set_planes_workaround()
11844 pipe_config->hsw_workaround_pipe = INVALID_PIPE; in haswell_mode_set_planes_workaround()
11846 if (!pipe_config->base.active || in haswell_mode_set_planes_workaround()
11847 needs_modeset(&pipe_config->base)) in haswell_mode_set_planes_workaround()
12026 struct intel_crtc_state *pipe_config = in intel_atomic_check() local
12048 ret = intel_modeset_pipe_config(crtc, pipe_config); in intel_atomic_check()
12051 pipe_config, "[failed]"); in intel_atomic_check()
12058 pipe_config, true)) { in intel_atomic_check()
12060 pipe_config->update_pipe = true; in intel_atomic_check()
12070 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, in intel_atomic_check()
12116 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); in intel_update_crtc() local
12121 dev_priv->display.crtc_enable(pipe_config, state); in intel_update_crtc()
12124 pipe_config); in intel_update_crtc()
12129 intel_crtc, pipe_config, in intel_update_crtc()