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Searched refs:_MMIO (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDi915_oa_hsw.c36 { _MMIO(0x2724), 0x00800000 },
37 { _MMIO(0x2720), 0x00000000 },
38 { _MMIO(0x2714), 0x00800000 },
39 { _MMIO(0x2710), 0x00000000 },
46 { _MMIO(0x9840), 0x00000080 },
47 { _MMIO(0x253a4), 0x01600000 },
48 { _MMIO(0x25440), 0x00100000 },
49 { _MMIO(0x25128), 0x00000000 },
50 { _MMIO(0x2691c), 0x00000800 },
51 { _MMIO(0x26aa0), 0x01500000 },
[all …]
HDi915_reg.h123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) macro
125 #define INVALID_MMIO_REG _MMIO(0)
145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
149 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
151 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
152 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
156 #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
158 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
[all …]
HDi915_guc_reg.h29 #define GUC_STATUS _MMIO(0xc000)
51 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
54 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
56 #define DMA_ADDR_0_LOW _MMIO(0xc300)
57 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
58 #define DMA_ADDR_1_LOW _MMIO(0xc308)
59 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
62 #define DMA_COPY_SIZE _MMIO(0xc310)
63 #define DMA_CTRL _MMIO(0xc314)
67 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
[all …]
HDintel_lrc.h33 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
34 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
35 #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
36 #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
40 #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
41 #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
42 #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
43 #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
HDi915_pvinfo.h110 _MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))
HDintel_guc.c41 return _MMIO(guc->send_regs.base + 4 * i); in guc_send_reg()
HDintel_csr.c382 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); in parse_csr_fw()
HDintel_i2c.c252 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + in intel_gpio_setup()