Lines Matching refs:_MMIO
29 #define GUC_STATUS _MMIO(0xc000)
51 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
54 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
56 #define DMA_ADDR_0_LOW _MMIO(0xc300)
57 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
58 #define DMA_ADDR_1_LOW _MMIO(0xc308)
59 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
62 #define DMA_COPY_SIZE _MMIO(0xc310)
63 #define DMA_CTRL _MMIO(0xc314)
67 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
71 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
73 #define HUC_STATUS2 _MMIO(0xD3B0)
77 #define GUC_WOPCM_SIZE _MMIO(0xc050)
85 #define GEN8_GT_PM_CONFIG _MMIO(0x138140)
86 #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
87 #define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
90 #define GEN8_GTCR _MMIO(0x4274)
93 #define GUC_ARAT_C6DIS _MMIO(0xA178)
95 #define GUC_SHIM_CONTROL _MMIO(0xc064)
112 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
115 #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
117 #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
119 #define DE_GUCRMR _MMIO(0x44054)
121 #define GUC_BCS_RCS_IER _MMIO(0xC550)
122 #define GUC_VCS2_VCS1_IER _MMIO(0xC554)
123 #define GUC_WD_VECS_IER _MMIO(0xC558)
124 #define GUC_PM_P24C_IER _MMIO(0xC55C)