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Searched refs:RREG32 (Results 1 – 25 of 105) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
HDradeon_bios.c287 bus_cntl = RREG32(R600_BUS_CNTL);
288 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
289 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
290 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
291 rom_cntl = RREG32(R600_ROM_CNTL);
335 viph_control = RREG32(RADEON_VIPH_CONTROL);
336 bus_cntl = RREG32(R600_BUS_CNTL);
337 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
338 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
339 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
[all …]
HDradeon_legacy_encoders.c55 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
83 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
86 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
91 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
186 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
189 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
196 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
207 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
277 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
352 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
[all …]
HDradeon_i2c.c129 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
135 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
138 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
142 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
145 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
149 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
151 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
153 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
155 temp = RREG32(rec->mask_data_reg); in pre_xfer()
168 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in post_xfer()
[all …]
HDrs600.c57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
115 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
132 … if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
148 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
226 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
235 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
[all …]
HDvce_v2_0.c43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
57 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
62 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
77 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
93 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
134 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
[all …]
HDvce_v1_0.c63 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
65 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
80 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
82 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
108 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
112 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
117 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
121 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
125 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
130 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
[all …]
HDr600.c117 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
139 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
173 *val = RREG32(reg); in r600_get_allowed_info_register()
342 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
787 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
801 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
805 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
809 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
813 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
818 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
[all …]
HDrv730_dpm.c203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
205 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
207 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
209 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
211 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
214 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
216 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
218 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
220 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
222 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
HDr100.c74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
168 … if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
[all …]
HDrs400.c151 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
155 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
242 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
257 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
271 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
284 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
307 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info()
309 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info()
322 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info()
325 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info()
[all …]
HDcik.c160 *val = RREG32(reg); in cik_get_allowed_info_register()
177 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
239 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
240 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
251 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
253 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1900 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1918 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1941 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1946 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
[all …]
HDevergreen.c52 r = RREG32(EVERGREEN_CG_IND_DATA); in eg_cg_rreg()
74 r = RREG32(EVERGREEN_PIF_PHY0_DATA); in eg_pif_phy0_rreg()
96 r = RREG32(EVERGREEN_PIF_PHY1_DATA); in eg_pif_phy1_rreg()
1089 *val = RREG32(reg); in evergreen_get_allowed_info_register()
1141 if (RREG32(status_reg) & DCLK_STATUS) in sumo_set_uvd_clock()
1154 u32 cg_scratch = RREG32(CG_SCRATCH1); in sumo_set_uvd_clocks()
1335 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1345 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1346 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1369 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
[all …]
HDni.c47 r = RREG32(TN_SMC_IND_DATA_0); in tn_smc_rreg()
649 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; in ni_mc_load_microcode()
650 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ni_mc_load_microcode()
654 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in ni_mc_load_microcode()
679 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) in ni_mc_load_microcode()
883 *val = RREG32(reg); in cayman_get_allowed_info_register()
1029 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in cayman_gpu_init()
1030 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in cayman_gpu_init()
1107 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in cayman_gpu_init()
1127 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in cayman_gpu_init()
[all …]
HDr420.c98 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); in r420_pipes_init()
133 tmp = RREG32(R300_DST_PIPE_CONFIG); in r420_pipes_init()
137 RREG32(R300_RB2D_DSTCACHE_MODE) | in r420_pipes_init()
146 tmp = RREG32(RV530_GB_PIPE_SELECT2); in r420_pipes_init()
165 r = RREG32(R_0001FC_MC_IND_DATA); in r420_mc_rreg()
283 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
315 RREG32(R_000E40_RBBM_STATUS), in r420_resume()
316 RREG32(R_0007C0_CP_STAT)); in r420_resume()
406 RREG32(R_000E40_RBBM_STATUS), in r420_init()
407 RREG32(R_0007C0_CP_STAT)); in r420_init()
[all …]
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgmc_v8_0.c180 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
198 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
324 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
347 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
353 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
393 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
417 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
432 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
467 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
472 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
[all …]
HDgmc_v7_0.c92 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
110 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
222 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
228 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
241 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v7_0_vram_gtt_location()
276 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
281 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
301 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
305 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
[all …]
HDamdgpu_i2c.c50 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in amdgpu_i2c_pre_xfer()
70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in amdgpu_i2c_pre_xfer()
72 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in amdgpu_i2c_pre_xfer()
76 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in amdgpu_i2c_post_xfer()
[all …]
HDcz_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
147 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
358 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
374 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_soft_reset()
[all …]
HDiceland_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
147 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
358 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
374 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_soft_reset()
[all …]
HDvce_v3_0.c91 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
93 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
95 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
123 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
125 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
127 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
183 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
188 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
193 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
198 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
[all …]
HDvce_v4_0.c66 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
68 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr()
70 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr()
88 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
92 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr()
131 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded()
167 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID)); in vce_v4_0_mmsch_start()
186 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); in vce_v4_0_mmsch_start()
190 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); in vce_v4_0_mmsch_start()
[all …]
HDamdgpu_amdkfd_gfx_v8.c263 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
336 value = RREG32(mmRLC_CP_SCHEDULERS); in kgd_hqd_load()
398 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
439 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
447 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
452 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
531 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
536 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
537 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
554 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
[all …]
HDuvd_v5_0.c59 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_ring_get_rptr()
73 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
366 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_start()
512 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
565 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v5_0_is_idle()
574 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) in uvd_v5_0_wait_for_idle()
615 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
616 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
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HDdce_v10_0.c178 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v10_0_audio_endpt_rreg()
200 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
238 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
249 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
258 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
259 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
281 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
305 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
340 … tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
346 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
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HDdce_v11_0.c196 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v11_0_audio_endpt_rreg()
218 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v11_0_vblank_get_counter()
256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
267 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
276 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
277 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
299 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v11_0_hpd_sense()
323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
358 … tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
364 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
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