Searched refs:misaligned_size (Results 1 – 6 of 6) sorted by relevance
278 int misaligned_size; in xge_hal_check_alignment() local280 misaligned_size = (int)(dma_pointer & (alignment - 1)); in xge_hal_check_alignment()281 if (!misaligned_size) { in xge_hal_check_alignment()286 misaligned_size = (int)(dma_pointer & (copy_size - 1)); in xge_hal_check_alignment()287 misaligned_size = copy_size - misaligned_size; in xge_hal_check_alignment()289 misaligned_size = size; in xge_hal_check_alignment()292 return misaligned_size; in xge_hal_check_alignment()
840 dma_addr_t dma_pointer, int size, int misaligned_size) in xge_hal_fifo_dtr_buffer_set_aligned() argument860 xge_assert(misaligned_size != 0 && in xge_hal_fifo_dtr_buffer_set_aligned()861 misaligned_size <= fifo->config->alignment_size); in xge_hal_fifo_dtr_buffer_set_aligned()863 remaining_size = size - misaligned_size; in xge_hal_fifo_dtr_buffer_set_aligned()867 vaddr, misaligned_size); in xge_hal_fifo_dtr_buffer_set_aligned()876 txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(misaligned_size); in xge_hal_fifo_dtr_buffer_set_aligned()877 txdl_priv->bytes_sent += misaligned_size; in xge_hal_fifo_dtr_buffer_set_aligned()890 misaligned_size, in xge_hal_fifo_dtr_buffer_set_aligned()898 misaligned_size; in xge_hal_fifo_dtr_buffer_set_aligned()
538 u32 misaligned_size; in vxge_hal_check_alignment() local540 misaligned_size = (int)(dma_pointer & (alignment - 1)); in vxge_hal_check_alignment()541 if (!misaligned_size) { in vxge_hal_check_alignment()546 misaligned_size = (int)(dma_pointer & (copy_size - 1)); in vxge_hal_check_alignment()547 misaligned_size = copy_size - misaligned_size; in vxge_hal_check_alignment()549 misaligned_size = size; in vxge_hal_check_alignment()552 return (misaligned_size); in vxge_hal_check_alignment()
1022 u32 misaligned_size) in vxge_hal_fifo_txdl_buffer_set_aligned() argument1034 (size != 0) && (misaligned_size != 0)); in vxge_hal_fifo_txdl_buffer_set_aligned()1047 misaligned_size); in vxge_hal_fifo_txdl_buffer_set_aligned()1064 vxge_assert(misaligned_size != 0 && in vxge_hal_fifo_txdl_buffer_set_aligned()1065 misaligned_size <= fifo->config->alignment_size); in vxge_hal_fifo_txdl_buffer_set_aligned()1067 remaining_size = size - misaligned_size; in vxge_hal_fifo_txdl_buffer_set_aligned()1071 vaddr, misaligned_size); in vxge_hal_fifo_txdl_buffer_set_aligned()1081 txdp->control_0 |= VXGE_HAL_FIFO_TXD_BUFFER_SIZE(misaligned_size); in vxge_hal_fifo_txdl_buffer_set_aligned()1082 txdl_priv->bytes_sent += misaligned_size; in vxge_hal_fifo_txdl_buffer_set_aligned()1095 misaligned_size, in vxge_hal_fifo_txdl_buffer_set_aligned()[all …]
329 dma_addr_t dma_pointer, int size, int misaligned_size);
2606 u32 misaligned_size);