Home
last modified time | relevance | path

Searched refs:isSExt (Results 1 – 23 of 23) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetCallingConv.h67 bool isSExt() const { return Flags & SExt; } in isSExt() function
HDTargetLowering.h2276 bool isSExt : 1; member
2286 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelDAGToDAG.cpp2446 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2449 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2455 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
2461 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2466 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
2482 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2485 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2493 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
2499 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
2504 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
[all …]
HDPPCISelLowering.cpp3004 if (Flags.isSExt()) in extendArgForPPC64()
4931 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
5501 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMSelectionDAGInfo.cpp101 Entry.isSExt = false; in EmitSpecializedLibcall()
HDARMFastISel.cpp2137 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
HDARMISelLowering.cpp6464 Entry.isSExt = false; in LowerFSINCOS()
6471 Entry.isSExt = false; in LowerFSINCOS()
11073 Entry.isSExt = isSigned; in LowerDivRem()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZCallingConv.td13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGBuilder.cpp671 bool isSExt = true; in getCopyFromRegs() local
674 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 in getCopyFromRegs()
676 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 in getCopyFromRegs()
678 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 in getCopyFromRegs()
680 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 in getCopyFromRegs()
682 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 in getCopyFromRegs()
684 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 in getCopyFromRegs()
686 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 in getCopyFromRegs()
688 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 in getCopyFromRegs()
694 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
[all …]
HDLegalizeDAG.cpp2071 Entry.isSExt = isSigned; in ExpandLibCall()
2119 Entry.isSExt = isSigned; in ExpandLibCall()
2153 Entry.isSExt = isSigned; in ExpandChainLibCall()
2281 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2290 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2386 Entry.isSExt = false; in ExpandSinCosLibCall()
2394 Entry.isSExt = false; in ExpandSinCosLibCall()
2402 Entry.isSExt = false; in ExpandSinCosLibCall()
HDLegalizeTypes.cpp1079 Entry.isSExt = isSigned; in ExpandChainLibCall()
HDTargetLowering.cpp72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); in setAttributes()
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); in makeLibCall()
HDLegalizeIntegerTypes.cpp2448 Entry.isSExt = true; in ExpandIntRes_XMULO()
2456 Entry.isSExt = true; in ExpandIntRes_XMULO()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp155 if (ArgFlags.isSExt()) in CC_Hexagon_VarArg()
192 if (ArgFlags.isSExt()) in CC_Hexagon()
273 if (ArgFlags.isSExt()) in RetCC_Hexagon()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp1296 if (Outs[OIdx].Flags.isSExt()) in LowerCall()
1309 else if (Outs[OIdx].Flags.isSExt()) in LowerCall()
2183 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2309 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86FastISel.cpp1042 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1048 if (Outs[0].Flags.isSExt()) in X86SelectRet()
2877 if (Flags.isSExt()) in fastLowerCall()
HDX86ISelLowering.cpp16943 Entry.isSExt = false; in LowerWin64_i128OP()
18402 Entry.isSExt = false; in LowerFSINCOS()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp312 if (ArgFlags.isSExt()) in AnalyzeArguments()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsFastISel.cpp1494 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
HDMipsISelLowering.cpp2373 if (ArgFlags.isSExt()) in CC_MipsO32()
2385 if (ArgFlags.isSExt()) in CC_MipsO32()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp617 Offset, Ins[i].Flags.isSExt()); in LowerFormalArguments()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64FastISel.cpp3747 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
HDAArch64ISelLowering.cpp1709 Entry.isSExt = false; in LowerFSINCOS()