Home
last modified time | relevance | path

Searched refs:i8 (Results 1 – 25 of 129) sorted by relevance

123456

/NextBSD/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
HDtst.signedkeyspos.d50 @i8["cat", (char)-2] = sum(-2);
51 @i8["dog", (char)-2] = sum(-22);
52 @i8["mouse", (char)-2] = sum(-222);
53 @i8["cat", (char)-1] = sum(-1);
54 @i8["dog", (char)-1] = sum(-11);
55 @i8["mouse", (char)-1] = sum(-111);
56 @i8["cat", (char)0] = sum(0);
57 @i8["dog", (char)0] = sum(10);
58 @i8["mouse", (char)0] = sum(100);
59 @i8["cat", (char)1] = sum(1);
[all …]
HDtst.signedkeys.d95 @i8[(char)-2] = sum(-2);
96 @i8[(char)-1] = sum(-1);
97 @i8[(char)0] = sum(0);
98 @i8[(char)1] = sum(1);
99 @i8[(char)2] = sum(2);
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrShiftRotate.td36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
50 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
90 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
102 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
108 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
112 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
[all …]
HDX86CallingConv.td27 // Scalar values are returned in AX first, then DX. For i8, the ABI
30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
32 // for functions that return two i8 values are currently expected to pack the
37 CCIfType<[i1], CCPromoteToType<i8>>,
38 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
102 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
132 CCIfType<[i8, i16], CCPromoteToType<i32>>,
179 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
188 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
255 // Promote i1/i8/i16 arguments to i32.
[all …]
HDX86InstrCompiler.td256 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
295 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
297 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
299 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
304 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
306 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
313 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
317 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
325 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
[all …]
HDX86ISelDAGToDAG.cpp289 return CurDAG->getTargetConstant(Imm, DL, MVT::i8); in getI8Imm()
826 SDValue Eight = DAG.getConstant(8, DL, MVT::i8); in FoldMaskAndShiftToExtract()
830 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8); in FoldMaskAndShiftToExtract()
980 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8); in FoldMaskAndShiftToScale()
982 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8); in FoldMaskAndShiftToScale()
1873 case MVT::i8: in SelectAtomicLoadArith()
2027 LdVT != MVT::i8) in isLoadIncOrDecStore()
2091 if (LdVT == MVT::i8) return X86::DEC8m; in getFusedLdStOpcode()
2097 if (LdVT == MVT::i8) return X86::INC8m; in getFusedLdStOpcode()
2262 CstVT = MVT::i8; in Select()
[all …]
HDX86SelectionDAGInfo.cpp135 AVT = MVT::i8; in EmitTargetCodeForMemset()
141 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
151 AVT = MVT::i8; in EmitTargetCodeForMemset()
180 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; in EmitTargetCodeForMemset()
236 AVT = MVT::i8; in EmitTargetCodeForMemcpy()
/NextBSD/sys/i386/i386/
HDbpf_jit_machdep.h202 #define ADDib(i8, r32) do { \ argument
205 emitm(&stream, i8, 1); \
222 #define SUBib(i8, r32) do { \ argument
225 emitm(&stream, i8, 1); \
241 #define ANDib(i8, r8) do { \ argument
248 emitm(&stream, i8, 1); \
306 #define SHLib(i8, r32) do { \ argument
309 emitm(&stream, i8, 1); \
319 #define SHRib(i8, r32) do { \ argument
322 emitm(&stream, i8, 1); \
/NextBSD/sys/amd64/amd64/
HDbpf_jit_machdep.h257 #define ADDib(i8, r32) do { \ argument
260 emitm(&stream, i8, 1); \
277 #define SUBib(i8, r64) do { \ argument
280 emitm(&stream, i8, 1); \
296 #define ANDib(i8, r8) do { \ argument
303 emitm(&stream, i8, 1); \
361 #define SHLib(i8, r32) do { \ argument
364 emitm(&stream, i8, 1); \
374 #define SHRib(i8, r32) do { \ argument
377 emitm(&stream, i8, 1); \
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
95 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
101 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
102 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
109 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
[all …]
HDMSP430CallingConv.td16 // i8 are returned in registers R15B, R14B, R13B, R12B
17 CCIfType<[i8], CCAssignToReg<[R15B, R14B, R13B, R12B]>>,
30 // Promote i8 arguments to i16.
31 CCIfType<[i8], CCPromoteToType<i16>>,
HDMSP430InstrInfo.td19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
32 SDTCisVT<1, i8>]>;
35 SDTCisVT<3, i8>]>;
90 def cc : Operand<i8> {
297 def def8 : PatLeaf<(i8 GR8:$src), [{
311 [(store (i8 imm:$src), addr:$dst)]>;
329 [(store (i8 (load addr:$src)), addr:$dst)]>;
406 [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
418 (i8 (load addr:$src))), addr:$dst),
480 [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
[all …]
/NextBSD/contrib/llvm/patches/
HDpatch-05-clang-r244063-missing-atomic-libcall.diff161 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 55, i32 5)
167 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_fetch_sub_4(i8* {{%[0-9]+}}, i32 55, i32 5)
173 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_fetch_and_4(i8* {{%[0-9]+}}, i32 55, i32 5)
179 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_fetch_or_4(i8* {{%[0-9]+}}, i32 55, i32 5)
185 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_fetch_xor_4(i8* {{%[0-9]+}}, i32 55, i32 5)
191 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_fetch_nand_4(i8* {{%[0-9]+}}, i32 55, i32 5)
197 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_add_fetch_4(i8* {{%[0-9]+}}, i32 55, i32 5)
203 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_sub_fetch_4(i8* {{%[0-9]+}}, i32 55, i32 5)
209 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_and_fetch_4(i8* {{%[0-9]+}}, i32 55, i32 5)
215 + // CHECK: {{%[^ ]*}} = tail call i32 @__atomic_or_fetch_4(i8* {{%[0-9]+}}, i32 55, i32 5)
[all …]
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDValueTypes.td24 def i8 : ValueType<8 , 2>; // 8-bit integer value
42 def v1i8 : ValueType<16, 19>; // 1 x i8 vector value
43 def v2i8 : ValueType<16 , 20>; // 2 x i8 vector value
44 def v4i8 : ValueType<32 , 21>; // 4 x i8 vector value
45 def v8i8 : ValueType<64 , 22>; // 8 x i8 vector value
46 def v16i8 : ValueType<128, 23>; // 16 x i8 vector value
47 def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
48 def v64i8 : ValueType<512, 25>; // 64 x i8 vector value
HDMachineValueType.h40 i8 = 2, // This is an 8 bit integer value enumerator
297 case v64i8: return i8; in getVectorElementType()
398 case i8 : in getSizeInBits()
514 return MVT::i8; in getIntegerVT()
538 case MVT::i8: in getVectorVT()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelDAGToDAG.cpp689 case MVT::i8: in SelectLoad()
717 case MVT::i8: in SelectLoad()
746 case MVT::i8: in SelectLoad()
769 case MVT::i8: in SelectLoad()
798 case MVT::i8: in SelectLoad()
821 case MVT::i8: in SelectLoad()
929 case MVT::i8: in SelectLoadVector()
953 case MVT::i8: in SelectLoadVector()
982 case MVT::i8: in SelectLoadVector()
1006 case MVT::i8: in SelectLoadVector()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMSA.txt72 bmz.v wd, ws, wt/i8 -> (vselect wt/i8, wd, ws)
73 bmnz.v wd, ws, wt/i8 -> (vselect wt/i8, ws, wd)
74 bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws)
HDMipsCallingConv.td78 // Promote i8/i16 arguments to i32.
79 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
93 // Promote i1/i8/i16 return values to i32.
94 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
129 CCIfType<[i8, i16, i32, i64],
134 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
165 CCIfType<[i8, i16, i32, i64],
170 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
199 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
201 CCIfType<[i8, i16, i32, i64],
[all …]
/NextBSD/contrib/netbsd-tests/include/
HDt_inttypes.c40 int8_t i8 = 0; in ATF_TC_BODY() local
74 PRINT(PRId8, i8); in ATF_TC_BODY()
89 PRINT(PRIi8, i8); in ATF_TC_BODY()
165 SCAN(SCNd8, i8); in ATF_TC_BODY()
180 SCAN(SCNi8, i8); in ATF_TC_BODY()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCFastISel.cpp283 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { in isLoadTypeLegal()
474 case MVT::i8: in PPCEmitLoad()
617 case MVT::i8: in PPCEmitStore()
822 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
841 case MVT::i8: in PPCEmitCmp()
1002 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && in SelectIToFP()
1024 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { in SelectIToFP()
1165 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1405 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) in finishCall()
1429 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { in finishCall()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td50 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
52 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
77 CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
131 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
133 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
158 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,
174 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
191 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
192 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
243 // Promote i8/i16/i32 arguments to i64.
[all …]
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp169 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
170 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
171 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
172 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
200 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
201 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
202 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
203 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
234 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, in getCastInstrCost()
HDARMCallingConv.td24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
42 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
102 // Promote i8/i16 arguments to i32.
103 CCIfType<[i8, i16], CCPromoteToType<i32>>,
115 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
132 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFCallingConv.td19 // Promote i8/i16/i32 args to i64
20 CCIfType<[ i8, i16, i32 ], CCPromoteToType<i64>>,
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreCallingConv.td28 // Promote i8/i16 arguments to i32.
29 CCIfType<[i8, i16], CCPromoteToType<i32>>,

123456