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Searched refs:gpu_addr (Results 1 – 20 of 20) sorted by relevance

/NextBSD/sys/dev/drm2/radeon/
HDevergreen_blit_kms.c43 int w, int h, u64 gpu_addr) in set_render_target() argument
61 radeon_ring_write(ring, gpu_addr >> 8); in set_render_target()
113 u64 gpu_addr; in set_shaders() local
116 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; in set_shaders()
119 radeon_ring_write(ring, gpu_addr >> 8); in set_shaders()
124 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; in set_shaders()
127 radeon_ring_write(ring, gpu_addr >> 8); in set_shaders()
132 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; in set_shaders()
133 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); in set_shaders()
138 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) in set_vtx_resource() argument
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HDr600_blit_kms.c41 int w, int h, u64 gpu_addr) in set_render_target() argument
59 radeon_ring_write(ring, gpu_addr >> 8); in set_render_target()
117 u64 gpu_addr; in set_shaders() local
124 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; in set_shaders()
127 radeon_ring_write(ring, gpu_addr >> 8); in set_shaders()
138 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; in set_shaders()
141 radeon_ring_write(ring, gpu_addr >> 8); in set_shaders()
155 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; in set_shaders()
156 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); in set_shaders()
161 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) in set_vtx_resource() argument
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HDradeon_cursor.c128 uint64_t gpu_addr) in radeon_set_cursor() argument
135 upper_32_bits(gpu_addr)); in radeon_set_cursor()
137 gpu_addr & 0xffffffff); in radeon_set_cursor()
141 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); in radeon_set_cursor()
143 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); in radeon_set_cursor()
146 gpu_addr & 0xffffffff); in radeon_set_cursor()
148 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; in radeon_set_cursor()
164 uint64_t gpu_addr; in radeon_crtc_cursor_set() local
192 &gpu_addr); in radeon_crtc_cursor_set()
201 radeon_set_cursor(crtc, obj, gpu_addr); in radeon_crtc_cursor_set()
HDr600_blit.c48 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) in set_render_target() argument
68 OUT_RING(gpu_addr >> 8); in set_render_target()
75 OUT_RING(gpu_addr >> 8); in set_render_target()
131 u64 gpu_addr; in set_shaders() local
149 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
158 OUT_RING(gpu_addr >> 8); in set_shaders()
171 OUT_RING((gpu_addr + 256) >> 8); in set_shaders()
187 R600_SH_ACTION_ENA, 512, gpu_addr); in set_shaders()
191 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) in set_vtx_resource() argument
197 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); in set_vtx_resource()
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HDradeon_semaphore.c56 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
104 rdev->ring[signaler].last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_sync_rings()
105 rdev->ring[waiter].last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_sync_rings()
HDradeon_object.h131 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
133 u64 max_offset, u64 *gpu_addr);
163 return sa_bo->manager->gpu_addr + sa_bo->soffset; in radeon_sa_bo_gpu_addr()
HDradeon_object.c223 u64 *gpu_addr) in radeon_bo_pin_restricted() argument
229 if (gpu_addr) in radeon_bo_pin_restricted()
230 *gpu_addr = radeon_bo_gpu_offset(bo); in radeon_bo_pin_restricted()
270 if (gpu_addr != NULL) in radeon_bo_pin_restricted()
271 *gpu_addr = radeon_bo_gpu_offset(bo); in radeon_bo_pin_restricted()
278 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) in radeon_bo_pin() argument
280 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); in radeon_bo_pin()
HDni.c925 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
966 (ib->gpu_addr & 0xFFFFFFFC)); in cayman_ring_ib_execute()
967 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1146 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1163 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1171 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
1246 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in cayman_dma_ring_ib_execute()
1247 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
1328 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
1330 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cayman_dma_resume()
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HDr600.c1076 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1235 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
2263 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2264 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2265 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2277 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2391 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
2393 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
2398 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
2534 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); in r600_dma_ring_test()
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HDradeon.h224 uint64_t gpu_addr; member
400 uint64_t gpu_addr; member
449 uint64_t gpu_addr; member
635 uint64_t gpu_addr; member
662 uint64_t gpu_addr; member
737 uint64_t gpu_addr; member
745 int w, int h, u64 gpu_addr);
750 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
753 u64 gpu_addr, u32 size);
913 uint64_t gpu_addr; member
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HDradeon_fence.c836 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index; in radeon_fence_driver_start_ring()
840 ring, (uintmax_t)rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr); in radeon_fence_driver_start_ring()
860 rdev->fence_drv[ring].gpu_addr = 0; in radeon_fence_driver_init_ring()
HDradeon_ring.c89 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; in radeon_ib_get()
91 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); in radeon_ib_get()
716 &ring->gpu_addr); in radeon_ring_init()
737 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; in radeon_ring_init()
HDsi.c1800 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in si_fence_ring_emit()
1862 (ib->gpu_addr & 0xFFFFFFFC)); in si_ring_ib_execute()
1863 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
2051 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
2069 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
2070 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
2082 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
2102 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
2103 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
2108 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
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HDradeon_gart.c157 uint64_t gpu_addr; in radeon_gart_table_vram_pin() local
164 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); in radeon_gart_table_vram_pin()
173 rdev->gart.table_addr = gpu_addr; in radeon_gart_table_vram_pin()
HDevergreen.c1566 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
1632 (ib->gpu_addr & 0xFFFFFFFC)); in evergreen_ring_ib_execute()
1633 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in evergreen_ring_ib_execute()
1776 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in evergreen_cp_resume()
1777 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
1778 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
1790 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in evergreen_cp_resume()
3392 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
3436 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
3437 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
HDradeon_sa.c118 r = radeon_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr); in radeon_sa_bo_manager_start()
HDr100.c1164 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); in r100_cp_init()
1165 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); in r100_cp_init()
1174 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); in r100_cp_init()
1175 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); in r100_cp_init()
3788 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
HDradeon_device.c267 &rdev->wb.gpu_addr); in radeon_wb_init()
HDrv770.c288 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in rv770_mc_program()
/NextBSD/sys/dev/drm/
HDr600_blit.c1202 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) in set_render_target() argument
1222 OUT_RING(gpu_addr >> 8); in set_render_target()
1229 OUT_RING(gpu_addr >> 8); in set_render_target()
1285 u64 gpu_addr; in set_shaders() local
1305 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
1314 OUT_RING(gpu_addr >> 8); in set_shaders()
1327 OUT_RING((gpu_addr + 256) >> 8); in set_shaders()
1343 R600_SH_ACTION_ENA, 512, gpu_addr); in set_shaders()
1347 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) in set_vtx_resource() argument
1353 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); in set_vtx_resource()
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