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Searched refs:bus_read_4 (Results 1 – 25 of 184) sorted by relevance

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/NextBSD/sys/arm/freescale/imx/
HDimx51_ccm.c214 ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); in imx51_get_clock()
220 ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); in imx51_get_clock()
237 ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); in imx51_get_clock()
242 ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); in imx51_get_clock()
248 ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); in imx51_get_clock()
254 cacrr = bus_read_4(ccm_softc->res[0], CCMC_CACRR); in imx51_get_clock()
259 cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR); in imx51_get_clock()
264 cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR); in imx51_get_clock()
284 cdcr = bus_read_4(ccm_softc->res[0], CCMC_CDCR); in imx51_get_clock()
289 cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR); in imx51_get_clock()
[all …]
/NextBSD/sys/powerpc/powermac/
HDatibl.c173 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
174 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_rreg()
176 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
179 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_rreg()
182 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
195 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
196 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_wreg()
202 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_wreg()
205 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
223 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); in atibl_setlevel()
[all …]
HDmacio.c403 fcr = bus_read_4(sc->sc_memr, HEATHROW_FCR); in macio_attach()
427 fcr1 = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); in macio_attach()
667 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); in macio_enable_wireless()
676 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); in macio_enable_wireless()
691 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); in macio_enable_wireless()
695 x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); in macio_enable_wireless()
/NextBSD/sys/mips/rt305x/
HDrt305x_gpio.h82 bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
86 (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) | \
87 (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\
88 (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO51_40_##n)) << 40))
97 bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) & ~GPIO_MASK(g))
100 bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g))
103 ((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \
/NextBSD/sys/sparc64/fhc/
HDfhc.c195 board = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_BSR); in fhc_attach()
214 (void)bus_read_4(sc->sc_memres[i], FHC_ICLR); in fhc_attach()
219 sc->sc_ign = bus_read_4(sc->sc_memres[FHC_IGN], 0x0); in fhc_attach()
221 ctrl = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL); in fhc_attach()
226 (void)bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL); in fhc_attach()
258 (u_long)bus_read_4(fica->fica_memres, FHC_IMAP), in fhc_attach()
259 (u_long)bus_read_4(fica->fica_memres, FHC_ICLR)); in fhc_attach()
268 INTINO(bus_read_4(fica->fica_memres, FHC_IMAP))), in fhc_attach()
366 (void)bus_read_4(fica->fica_memres, FHC_IMAP); in fhc_intr_enable()
376 (void)bus_read_4(fica->fica_memres, FHC_IMAP); in fhc_intr_disable()
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/NextBSD/sys/arm/ti/omap4/
HDomap4_prcm_clks.c536 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_activate()
547 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_activate()
602 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_deactivate()
668 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_generic_accessible()
790 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_gptimer_get_source_freq()
848 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_hsmmc_set_source()
904 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); in omap4_clk_hsmmc_get_source_freq()
949 clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET); in omap4_clk_get_sysclk_freq()
1010 clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU); in omap4_clk_get_arm_fclk_freq()
1106 clksel = bus_read_4(clk_mem_res, clksel_reg_off); in omap4_clk_hsusbhost_activate()
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/NextBSD/sys/arm/broadcom/bcm2835/
HDbcm2836.c132 reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_PENDING(cpu)); in bcm2836_get_next_irq()
153 reg = bus_read_4(softc->sc_mem, in bcm2836_mask_irq()
163 reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu)); in bcm2836_mask_irq()
181 reg = bus_read_4(softc->sc_mem, in bcm2836_unmask_irq()
191 reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu)); in bcm2836_unmask_irq()
HDbcm2835_dma.c171 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); in bcm_dma_reset()
179 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); in bcm_dma_reset()
515 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); in bcm_dma_reg_dump()
600 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); in bcm_dma_intr()
613 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); in bcm_dma_intr()
/NextBSD/sys/dev/acpica/
HDacpi_hpet.c140 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); in hpet_get_timecount()
148 val = bus_read_4(sc->mem_res, HPET_CONFIG); in hpet_enable()
162 val = bus_read_4(sc->mem_res, HPET_CONFIG); in hpet_disable()
190 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_start()
208 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_start()
254 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + in hpet_intr_single()
264 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); in hpet_intr_single()
284 val = bus_read_4(sc->mem_res, HPET_ISR); in hpet_intr()
455 val = bus_read_4(sc->mem_res, HPET_PERIOD); in hpet_attach()
464 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); in hpet_attach()
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/NextBSD/sys/powerpc/mpc85xx/
HDqoriq_gpio.c140 reg = bus_read_4(sc->sc_mem, GPIO_GPDIR); in qoriq_gpio_pin_setflags()
145 reg = bus_read_4(sc->sc_mem, GPIO_GPDIR); in qoriq_gpio_pin_setflags()
148 reg = bus_read_4(sc->sc_mem, GPIO_GPODR); in qoriq_gpio_pin_setflags()
173 outvals = bus_read_4(sc->sc_mem, GPIO_GPDAT); in qoriq_gpio_pin_set()
192 *value = (bus_read_4(sc->sc_mem, GPIO_GPDAT) >> (31 - pin)) & 1; in qoriq_gpio_pin_get()
209 val = bus_read_4(sc->sc_mem, GPIO_GPDAT); in qoriq_gpio_pin_toggle()
HDmpc85xx_gpio.c134 outvals = bus_read_4(sc->out_res, 0); in mpc85xx_gpio_pin_set()
153 *value = (bus_read_4(sc->in_res, 0) >> (31 - pin)) & 1; in mpc85xx_gpio_pin_get()
170 val = bus_read_4(sc->out_res, 0); in mpc85xx_gpio_pin_toggle()
/NextBSD/sys/powerpc/powerpc/
HDopenpic.c392 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG); in openpic_suspend()
394 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i)); in openpic_suspend()
398 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i)); in openpic_suspend()
402 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i)); in openpic_suspend()
403 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i)); in openpic_suspend()
404 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i)); in openpic_suspend()
405 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i)); in openpic_suspend()
410 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY; in openpic_suspend()
423 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG); in openpic_resume()
/NextBSD/sys/dev/qlxgb/
HDqla_reg.h231 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
237 bus_read_4((ha->pci_reg), reg);\
249 bus_read_4((ha->pci_reg), off);\
/NextBSD/sys/arm/amlogic/aml8726/
HDaml8726_pinctrl.c85 #define MUX_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
88 #define PUD_READ_4(sc, reg) bus_read_4((sc)->res[1], reg)
91 #define PEN_READ_4(sc, reg) bus_read_4((sc)->res[2], reg)
94 #define AOMUX_READ_4(sc, reg) bus_read_4((sc)->res[3], reg)
97 #define AOPUD_READ_4(sc, reg) bus_read_4((sc)->res[4], reg)
100 #define AOPEN_READ_4(sc, reg) bus_read_4((sc)->res[5], reg)
HDaml8726_identsoc.c105 aml8726_soc_hw_rev = bus_read_4(&res, AML_SOC_HW_REV_REG); in aml8726_identify_soc()
107 aml8726_soc_metal_rev = bus_read_4(&res, AML_SOC_METAL_REV_REG); in aml8726_identify_soc()
HDaml8726_mp.c145 #define SCU_READ_4(reg) bus_read_4(&aml8726_smp.scu_res, (reg))
151 #define CPUCONF_READ_4(reg) bus_read_4(&aml8726_smp.cpucfg_res, \
158 #define AOBUS_READ_4(reg) bus_read_4(&aml8726_smp.aobus_res, \
165 #define CBUS_READ_4(reg) bus_read_4(&aml8726_smp.cbus_res, \
HDaml8726_fb.c118 #define CAV_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
123 #define VIU_READ_4(sc, reg) bus_read_4((sc)->res[1], reg)
126 #define VPP_READ_4(sc, reg) bus_read_4((sc)->res[2], reg)
129 #define CLK_READ_4(sc, reg) bus_read_4((sc)->res[X], reg)
/NextBSD/sys/dev/sound/macio/
HDdavbus.c182 bus_read_4(d->reg, DAVBUS_CODEC_STATUS))); in burgundy_init()
220 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & in burgundy_write_locked()
349 bus_read_4(d->reg, DAVBUS_CODEC_STATUS))); in screamer_init()
383 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY) in screamer_write_locked()
391 while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY) in screamer_write_locked()
584 reg = bus_read_4(d->reg, DAVBUS_SOUND_CTRL); in davbus_cint()
587 status = bus_read_4(d->reg, DAVBUS_CODEC_STATUS); in davbus_cint()
/NextBSD/sys/dev/mly/
HDmlyvar.h244 #define MLY_GET_REG4(sc, reg) bus_read_4 (sc->mly_regs_resource, reg)
255 *((u_int32_t *)ptr) = bus_read_4(sc->mly_regs_resource, mbox); \
256 *((u_int32_t *)ptr + 1) = bus_read_4(sc->mly_regs_resource, mbox + 4); \
257 *((u_int32_t *)ptr + 2) = bus_read_4(sc->mly_regs_resource, mbox + 8); \
258 *((u_int32_t *)ptr + 3) = bus_read_4(sc->mly_regs_resource, mbox + 12); \
/NextBSD/sys/dev/terasic/mtl/
HDterasic_mtl_reg.c89 v = bus_read_4(sc->mtl_reg_res, offset); in terasic_mtl_reg_read()
145 *blendp = le32toh(bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND)); in terasic_mtl_reg_blend_get()
228 v = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR); in terasic_mtl_reg_textcursor_get()
259 addr = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR); in terasic_mtl_reg_textframebufaddr_get()
/NextBSD/sys/dev/twe/
HDtwe_compat.h75 #define TWE_STATUS(sc) (u_int32_t)bus_read_4((sc)->twe_io, 0x4)
77 #define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_read_4((sc)->twe_io, 0xc)
/NextBSD/sys/arm/mv/
HDmv_ts.c107 ret = bus_read_4(sc->sc_res[0], 0); in ts_sysctl_handler()
114 ret = bus_read_4(sc->sc_res[0], 0); in ts_sysctl_handler()
/NextBSD/sys/dev/iir/
HDiir_pci.c230 if (bus_read_4(gdt->sc_dpmem, GDT_MPR_IC) != htole32(GDT_MPR_MAGIC)) { in iir_pci_attach()
261 protocol = (uint8_t)le32toh(bus_read_4(gdt->sc_dpmem, in iir_pci_attach()
415 ctx->info = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO); in gdt_mpr_intr()
417 ctx->info2 = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO + sizeof (u_int32_t)); in gdt_mpr_intr()
/NextBSD/sys/dev/agp/
HDagp_i810.c963 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i810_dump_regs()
974 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i830_dump_regs()
985 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i855_dump_regs()
996 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); in agp_i915_dump_regs()
1009 bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2)); in agp_i965_dump_regs()
1022 bus_read_4(sc->sc_res[0], AGP_SNB_GFX_MODE)); in agp_sb_dump_regs()
1091 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & in agp_i915_get_stolen_size()
1338 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); in agp_i965_get_gtt_total_entries()
1375 pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2); in agp_gen5_adjust_pgtbl_size()
1380 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); in agp_gen5_adjust_pgtbl_size()
[all …]
/NextBSD/sys/arm/versatile/
HDversatile_pci.c98 bus_read_4(sc->mem_res[MEM_SYS], (reg))
103 bus_read_4(sc->mem_res[MEM_CORE], (reg))
108 bus_read_4(sc->mem_res[MEM_BASE], (reg))
113 bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))

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