Lines Matching refs:bus_read_4
173 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
174 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_rreg()
176 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
179 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_rreg()
182 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
195 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
196 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); in atibl_pll_wreg()
202 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_wreg()
205 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
223 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); in atibl_setlevel()
227 disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN); in atibl_setlevel()
230 lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL); in atibl_setlevel()
270 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); in atibl_getlevel()