| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMCallingConv.h | 35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in f64AssignAPCS() 42 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, in f64AssignAPCS() 50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in f64AssignAPCS() 52 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, in f64AssignAPCS() 91 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, in f64AssignAAPCS() 106 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in f64AssignAAPCS() 107 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64AssignAAPCS() 138 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in f64RetAssign() 139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], in f64RetAssign() 237 State.addLoc(*It); in CC_ARM_AAPCS_Custom_Aggregate() [all …]
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64CallingConvention.h | 56 State.addLoc(It); in finishStackBlock() 121 State.addLoc(It); in CC_AArch64_Custom_Block()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 149 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); in CC_Hexagon_VarArg() 164 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); in CC_Hexagon_VarArg() 169 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); in CC_Hexagon_VarArg() 185 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in CC_Hexagon() 229 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Hexagon32() 234 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in CC_Hexagon32() 243 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Hexagon64() 254 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Hexagon64() 259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in CC_Hexagon64() 306 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in RetCC_Hexagon32() [all …]
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | CallingConvLower.cpp | 57 addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in HandleByVal()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, in CC_Sparc_Assign_SRet() 61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Sparc_Assign_f64() 64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, in CC_Sparc_Assign_f64() 72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Sparc_Assign_f64() 74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, in CC_Sparc_Assign_f64() 109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Sparc64_Full() 119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in CC_Sparc64_Full() 134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, in CC_Sparc64_Half() 147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, in CC_Sparc64_Half() 150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_Sparc64_Half() [all …]
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | CallingConvLower.h | 264 void addLoc(const CCValAssign &V) { in addLoc() function
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelLowering.cpp | 332 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); in AnalyzeArguments()
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsISelLowering.cpp | 2438 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in CC_MipsO32() 2440 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_MipsO32()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUISelLowering.cpp | 79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); in allocateStack()
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