| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMTargetTransformInfo.cpp | 409 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
413 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
417 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
421 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
426 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
430 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
434 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
438 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
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| /NextBSD/contrib/llvm/lib/Target/WebAssembly/ |
| HD | WebAssemblyInstrInteger.td | 20 defm SREM : BinaryInt<srem>;
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 191 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsFastISel.cpp | 1661 case ISD::SREM: in selectDivRem()
1682 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1785 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
1786 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
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| HD | MipsSEISelLowering.cpp | 170 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
217 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
267 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2010 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| HD | MipsISelLowering.cpp | 314 setOperationAction(ISD::SREM, MVT::i32, Expand); in MipsTargetLowering()
318 setOperationAction(ISD::SREM, MVT::i64, Expand); in MipsTargetLowering()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 173 case ISD::SREM: return "srem"; in getOperationName()
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| HD | SelectionDAGBuilder.h | 773 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
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| HD | LegalizeVectorOps.cpp | 266 case ISD::SREM: in LegalizeOp()
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| HD | SelectionDAG.cpp | 2387 case ISD::SREM: in computeKnownBits()
3197 case ISD::SREM: in FoldValue()
3358 case ISD::SREM: in getNode()
3714 case ISD::SREM: in getNode()
3742 case ISD::SREM: in getNode()
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| HD | LegalizeVectorTypes.cpp | 118 case ISD::SREM: in ScalarizeVectorResult()
675 case ISD::SREM: in SplitVectorResult()
1964 case ISD::SREM: in WidenVectorResult()
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| HD | LegalizeDAG.cpp | 2230 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; in useDivRem()
3560 case ISD::SREM: { in ExpandNode()
3562 bool isSigned = Node->getOpcode() == ISD::SREM; in ExpandNode()
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| HD | LegalizeIntegerTypes.cpp | 117 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; in PromoteIntegerResult()
1276 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; in ExpandIntegerResult()
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| HD | FastISel.cpp | 1516 return selectBinaryOp(I, ISD::SREM); in selectOperator()
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| HD | DAGCombiner.cpp | 1336 case ISD::SREM: return visitSREM(N); in visit()
2312 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::SREM, SDLoc(N), VT, in visitSREM()
2617 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); in visitSDIVREM()
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelLowering.cpp | 159 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
165 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/BPF/ |
| HD | BPFISelLowering.cpp | 119 setOperationAction(ISD::SREM, MVT::i64, Expand); in BPFTargetLowering()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 905 case ISD::SREM: in canOpTrap()
1559 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 1423 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, in HexagonTargetLowering()
1481 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC, in HexagonTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64FastISel.cpp | 4476 case ISD::SREM: in selectRem()
4924 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
4925 return selectRem(I, ISD::SREM); in fastSelectInstruction()
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| HD | AArch64ISelLowering.cpp | 255 setOperationAction(ISD::SREM, MVT::i32, Expand); in AArch64TargetLowering()
256 setOperationAction(ISD::SREM, MVT::i64, Expand); in AArch64TargetLowering()
677 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 1411 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1418 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUISelLowering.cpp | 279 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
350 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 361 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 147 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
149 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
442 setOperationAction(ISD::SREM, VT, Expand); in PPCTargetLowering()
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