| /NextBSD/crypto/openssl/crypto/cast/ |
| HD | cast_lcl.h | 154 # define ROTL(a,n) (_lrotl(a,n)) macro
156 # define ROTL(a,n) ((((a)<<(n))&0xffffffffL)|((a)>>((32-(n))&31))) macro
158 # define ROTL(a,n) ((((a)<<(n))&0xffffffffL)|((a)>>(32-(n)))) macro
174 t=ROTL(t,i); \
191 w=ROTL(w,i); \
211 t=ROTL(t,(key[n*2+1])); \
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| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZSelectionDAGInfo.cpp | 181 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, in addIPMSequence() local
183 return ROTL; in addIPMSequence()
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| HD | SystemZISelDAGToDAG.cpp | 792 case ISD::ROTL: { in expandRxSBG()
1193 case ISD::ROTL: in Select()
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| HD | SystemZISelLowering.cpp | 334 setOperationAction(ISD::ROTL, VT, Expand); in SystemZTargetLowering()
3089 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift); in lowerATOMIC_LOAD_OP()
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| /NextBSD/crypto/openssl/crypto/bn/asm/ |
| HD | ppc.pl | 126 $ROTL= "rotlwi"; # rotate left by immediate
150 $ROTL= "rotldi"; # rotate left by immediate
1719 $ROTL r3,r11,`$BITS/2` # rotate by $BITS/2 and store in r3
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 332 SHL, SRA, SRL, ROTL, ROTR, enumerator
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 185 case ISD::ROTL: return "rotl"; in getOperationName()
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| HD | LegalizeVectorOps.cpp | 279 case ISD::ROTL: in LegalizeOp()
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| HD | DAGCombiner.cpp | 1353 case ISD::ROTL: return visitRotate(N); in visit()
3455 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) in MatchBSwapHWord()
3456 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt); in MatchBSwapHWord()
3866 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); in MatchRotate()
3909 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
3952 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL); in MatchRotate()
3957 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL); in MatchRotate()
4107 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL in visitXOR()
4110 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT), in visitXOR()
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| HD | SelectionDAG.cpp | 2598 case ISD::ROTL: in ComputeNumSignBits()
3183 case ISD::ROTL: return std::make_pair(C1.rotl(C2), true); in FoldValue()
3416 case ISD::ROTL: in getNode()
6820 case ISD::ROTL: in UnrollVectorOp()
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| HD | LegalizeIntegerTypes.cpp | 887 case ISD::ROTL: in PromoteIntegerOperand()
2616 case ISD::ROTL: in ExpandIntegerOperand()
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| HD | LegalizeDAG.cpp | 1320 case ISD::ROTL: in LegalizeOp()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXISelLowering.cpp | 171 setOperationAction(ISD::ROTL, MVT::i64, Legal); in NVPTXTargetLowering()
174 setOperationAction(ISD::ROTL, MVT::i64, Expand); in NVPTXTargetLowering()
178 setOperationAction(ISD::ROTL, MVT::i32, Legal); in NVPTXTargetLowering()
181 setOperationAction(ISD::ROTL, MVT::i32, Expand); in NVPTXTargetLowering()
185 setOperationAction(ISD::ROTL, MVT::i16, Expand); in NVPTXTargetLowering()
187 setOperationAction(ISD::ROTL, MVT::i8, Expand); in NVPTXTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelLowering.cpp | 101 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
103 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/BPF/ |
| HD | BPFISelLowering.cpp | 133 setOperationAction(ISD::ROTL, MVT::i64, Expand); in BPFTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelDAGToDAG.cpp | 444 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
868 case ISD::ROTL: in getValueBits()
1916 case ISD::ROTL: in SelectBitPermutation()
2539 N->getOperand(0).getOpcode() != ISD::ROTL) { in Select()
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| HD | PPCInstr64Bit.td | 1191 // ROTL
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUISelLowering.cpp | 302 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AMDGPUTargetLowering()
303 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AMDGPUTargetLowering()
343 setOperationAction(ISD::ROTL, VT, Expand); in AMDGPUTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86InstrShiftRotate.td | 852 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
857 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 1424 ISD::ROTL, ISD::ROTR, ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, in HexagonTargetLowering()
1485 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcISelLowering.cpp | 1482 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1536 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 368 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsISelLowering.cpp | 347 setOperationAction(ISD::ROTL, MVT::i32, Expand); in MipsTargetLowering()
348 setOperationAction(ISD::ROTL, MVT::i64, Expand); in MipsTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreISelLowering.cpp | 114 setOperationAction(ISD::ROTL , MVT::i32, Expand); in XCoreTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 235 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AArch64TargetLowering()
236 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AArch64TargetLowering()
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