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Searched refs:RC (Results 1 – 25 of 273) sorted by relevance

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/NextBSD/contrib/ofed/libibverbs/include/infiniband/
HDopcode.h83 IBV_OPCODE(RC, SEND_FIRST),
84 IBV_OPCODE(RC, SEND_MIDDLE),
85 IBV_OPCODE(RC, SEND_LAST),
86 IBV_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
87 IBV_OPCODE(RC, SEND_ONLY),
88 IBV_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
89 IBV_OPCODE(RC, RDMA_WRITE_FIRST),
90 IBV_OPCODE(RC, RDMA_WRITE_MIDDLE),
91 IBV_OPCODE(RC, RDMA_WRITE_LAST),
92 IBV_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in mask() local
83 unsigned ID = RC->getID(); in mask()
203 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
205 assert(RW <= RC.width()); in evaluate()
206 return eXTR(RC, 0, RW); in evaluate()
209 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate() argument
211 uint16_t W = RC.width(); in evaluate()
213 return eXTR(RC, W-RW, W); in evaluate()
216 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate() argument
218 assert(N*16+16 <= RC.width()); in evaluate()
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HDBitTracker.h51 void put(RegisterRef RR, const RegisterCell &RC);
268 bool meet(const RegisterCell &RC, unsigned SelfR);
269 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
273 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
277 bool operator== (const RegisterCell &RC) const;
278 bool operator!= (const RegisterCell &RC) const {
279 return !operator==(RC);
282 const RegisterCell &operator=(const RegisterCell &RC) {
283 Bits = RC.Bits;
303 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
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HDBitTracker.cpp105 raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { in operator <<() argument
106 unsigned n = RC.Bits.size(); in operator <<()
116 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) { in operator <<()
117 const BT::BitValue &V = RC[i]; in operator <<()
118 const BT::BitValue &SV = RC[Start]; in operator <<()
155 OS << "]:" << RC[Start]; in operator <<()
158 const BT::BitValue &SV = RC[Start]; in operator <<()
184 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) { in meet() argument
190 const BitValue &RCV = RC[i]; in meet()
198 BT::RegisterCell &BT::RegisterCell::insert(const BT::RegisterCell &RC, in insert() argument
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/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName() argument
30 if (RC == &NVPTX::Float32RegsRegClass) { in getNVPTXRegClassName()
33 if (RC == &NVPTX::Float64RegsRegClass) { in getNVPTXRegClassName()
35 } else if (RC == &NVPTX::Int64RegsRegClass) { in getNVPTXRegClassName()
37 } else if (RC == &NVPTX::Int32RegsRegClass) { in getNVPTXRegClassName()
39 } else if (RC == &NVPTX::Int16RegsRegClass) { in getNVPTXRegClassName()
41 } else if (RC == &NVPTX::Int1RegsRegClass) { in getNVPTXRegClassName()
43 } else if (RC == &NVPTX::SpecialRegsRegClass) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr() argument
52 if (RC == &NVPTX::Float32RegsRegClass) { in getNVPTXRegClassStr()
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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDRegisterClassInfo.h67 void compute(const TargetRegisterClass *RC) const;
70 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
71 const RCInfo &RCI = RegClass[RC->getID()]; in get()
73 compute(RC); in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() argument
87 return get(RC).NumRegs; in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() argument
94 return get(RC); in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
104 return get(RC).ProperSubClass; in isProperSubClass()
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/NextBSD/sys/ofed/include/rdma/
HDib_pack.h106 IB_OPCODE(RC, SEND_FIRST),
107 IB_OPCODE(RC, SEND_MIDDLE),
108 IB_OPCODE(RC, SEND_LAST),
109 IB_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
110 IB_OPCODE(RC, SEND_ONLY),
111 IB_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
112 IB_OPCODE(RC, RDMA_WRITE_FIRST),
113 IB_OPCODE(RC, RDMA_WRITE_MIDDLE),
114 IB_OPCODE(RC, RDMA_WRITE_LAST),
115 IB_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true); in createLRSpillSlot()
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createLRSpillSlot()
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createFPSpillSlot()
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createEHSpillSlot()
68 EHSpillSlot[1] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); in createEHSpillSlot()
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetRegisterInfo.cpp88 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
89 if (!RC || RC->isAllocatable()) in getAllocatableClass()
90 return RC; in getAllocatableClass()
92 const unsigned *SubClass = RC->getSubClassMask(); in getAllocatableClass()
119 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
120 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && in getMinimalPhysRegClass()
121 (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
122 BestRC = RC; in getMinimalPhysRegClass()
132 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC() argument
133 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
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HDRegisterClassInfo.cpp79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { in compute()
80 assert(RC && "no register class given"); in compute()
81 RCInfo &RCI = RegClass[RC->getID()]; in compute()
84 unsigned NumRegs = RC->getNumRegs(); in compute()
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
135 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
157 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
172 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
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HDLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval() argument
68 S2RCMap.insert(std::make_pair(Slot, RC)); in getOrCreateInterval()
72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); in getOrCreateInterval()
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
85 if (RC) in print()
86 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
/NextBSD/contrib/llvm/utils/TableGen/
HDRegisterInfoEmitter.cpp116 for (const auto &RC : RegisterClasses) in runEnums() local
117 OS << " " << RC.getName() << "RegClassID" in runEnums()
118 << " = " << RC.EnumValue << ",\n"; in runEnums()
182 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
183 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
188 RC.buildRegUnitSet(RegUnits); in EmitRegUnitPressure()
192 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
957 for (const auto &RC : RegisterClasses) { in runMCDesc() local
958 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
961 std::string Name = RC.getName(); in runMCDesc()
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HDCodeGenRegisters.cpp856 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
857 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
858 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
863 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
865 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
869 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
873 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) in computeSubClasses()
874 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
878 for (auto &RC : RegClasses) { in computeSubClasses() local
879 const BitVector &SC = RC.getSubClasses(); in computeSubClasses()
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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetRegisterInfo.h127 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass() argument
128 return RC != this && hasSubClassEq(RC); in hasSubClass()
133 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() argument
134 unsigned ID = RC->getID(); in hasSubClassEq()
140 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass() argument
141 return RC->hasSubClass(this); in hasSuperClass()
146 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() argument
147 return RC->hasSubClassEq(this); in hasSuperClassEq()
323 getAllocatableClass(const TargetRegisterClass *RC) const;
329 const TargetRegisterClass *RC = nullptr) const;
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/NextBSD/contrib/ofed/management/opensm/scripts/
HDredhat-opensm.init.in165 RC=$?
166 [ $RC -eq 0 ] && echo_success || echo_failure
167 [ $RC -eq 0 ] && touch /var/lock/subsys/opensm
171 return $RC
219 RC=$?
220 [ $RC -eq 0 ] && echo_failure || echo_success
222 RC=$((! $RC))
227 RC=1
233 return $RC
291 RC=$?
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrFMA.td131 RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
135 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
136 (ins RC:$src1, RC:$src2, RC:$src3),
139 [(set RC:$dst,
140 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
143 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
144 (ins RC:$src1, RC:$src2, x86memop:$src3),
147 [(set RC:$dst,
148 (OpVT (OpNode RC:$src2, RC:$src1,
155 SDNode OpNode, RegisterClass RC, ValueType OpVT,
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HDX86InstrAVX512.td23 RegisterClass RC = rc;
62 // Size of RC in bits, e.g. 512 for VR512.
131 // "x" in v32i8x_info means RC = VR256X
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
227 [(set _.RC:$dst,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsCondMov.td36 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
38 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
40 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
48 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
50 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
271 class Select_Pseudo<RegisterOperand RC> :
272 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
273 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
276 class SelectFP_Pseudo_T<RegisterOperand RC> :
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HDMipsMachineFunction.cpp77 const TargetRegisterClass *RC = in getGlobalBaseReg() local
87 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); in getGlobalBaseReg()
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; in getMips16SPAliasReg() local
99 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); in getMips16SPAliasReg()
104 const TargetRegisterClass *RC = in createEhDataRegsFI() local
109 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), in createEhDataRegsFI()
110 RC->getAlignment(), false); in createEhDataRegsFI()
137 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI() argument
140 RC->getSize(), RC->getAlignment(), false); in getMoveF64ViaSpillFI()
HDMipsSEFrameLowering.cpp155 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
156 unsigned VR = MRI.createVirtualRegister(RC); in expandLoadCCond()
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
171 unsigned VR = MRI.createVirtualRegister(RC); in expandStoreCCond()
176 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
189 unsigned VR0 = MRI.createVirtualRegister(RC); in expandLoadACC()
190 unsigned VR1 = MRI.createVirtualRegister(RC); in expandLoadACC()
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
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HDMipsInstrFPU.td104 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
106 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
163 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
165 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
166 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
172 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
174 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
175 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
180 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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HDMipsSEInstrInfo.cpp182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, in storeRegToStack() argument
190 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
192 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
194 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
196 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
198 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
200 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
202 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
206 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIFixSGPRCopies.cpp140 const TargetRegisterClass *RC in inferRegClassFromUses() local
145 RC = TRI->getSubRegClass(RC, SubReg); in inferRegClassFromUses()
150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, in inferRegClassFromUses()
157 return RC; in inferRegClassFromUses()
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef() local
167 return TRI->getSubRegClass(RC, SubReg); in inferRegClassFromDef()
232 const TargetRegisterClass *RC in runOnMachineFunction() local
235 MRI.constrainRegClass(Op.getReg(), RC); in runOnMachineFunction()
238 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, in runOnMachineFunction() local
240 if (TRI->getCommonSubClass(RC, &AMDGPU::VGPR_32RegClass)) { in runOnMachineFunction()
HDSIRegisterInfo.h54 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
55 if (!RC) in isSGPRClass()
58 return !hasVGPRs(RC); in isSGPRClass()
70 bool hasVGPRs(const TargetRegisterClass *RC) const;
79 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
123 const TargetRegisterClass *RC) const;
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDResourcePriorityQueue.cpp369 const TargetRegisterClass *RC = *I; in regPressureDelta() local
370 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
376 const TargetRegisterClass *RC = *I; in regPressureDelta() local
377 if ((RegPressure[RC->getID()] + in regPressureDelta()
378 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
379 (RegPressure[RC->getID()] + in regPressureDelta()
380 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
381 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
490 if (RC) in scheduledNode()
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1234567891011