| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.h | 504 ISD::MemIndexedMode &AM, bool &IsInc,
507 ISD::MemIndexedMode &AM,
510 SDValue &Offset, ISD::MemIndexedMode &AM,
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| HD | AArch64ISelLowering.cpp | 9076 ISD::MemIndexedMode &AM, in getIndexedAddressParts()
9098 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
9120 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { in getPostIndexedAddressParts()
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| HD | AArch64ISelDAGToDAG.cpp | 987 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectIndexedLoad()
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 761 enum MemIndexedMode { enum
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| HD | SelectionDAGNodes.h | 663 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1910 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
1926 ISD::MemIndexedMode getAddressingMode() const {
1927 return ISD::MemIndexedMode((SubclassData >> 2) & 7);
1946 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1974 SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
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| HD | SelectionDAG.h | 846 SDValue Offset, ISD::MemIndexedMode AM);
847 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
854 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
874 SDValue Offset, ISD::MemIndexedMode AM);
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelLowering.h | 172 ISD::MemIndexedMode &AM,
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| HD | MSP430ISelDAGToDAG.cpp | 301 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
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| HD | MSP430ISelLowering.cpp | 1111 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.h | 310 ISD::MemIndexedMode &AM,
317 SDValue &Offset, ISD::MemIndexedMode &AM,
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| HD | ARMISelDAGToDAG.cpp | 813 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
849 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
869 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
948 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
1043 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1372 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1471 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectARMIndexedLoad()
1544 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectT2IndexedLoad()
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| HD | ARMISelLowering.cpp | 10603 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
10642 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.h | 178 ISD::MemIndexedMode &AM,
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| HD | HexagonISelDAGToDAG.cpp | 464 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
555 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
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| HD | HexagonISelLowering.cpp | 705 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 826 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
836 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
862 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
868 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
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| HD | TargetLowering.h | 2039 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
2050 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 345 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
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| HD | SelectionDAG.cpp | 580 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, in encodeMemSDNodeFlags()
4906 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
4939 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
5031 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedLoad()
5166 SDValue Offset, ISD::MemIndexedMode AM) { in getIndexedStore()
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| HD | DAGCombiner.cpp | 9200 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
9427 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
9507 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SplitIndexingFromLoad()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.h | 452 ISD::MemIndexedMode &AM,
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| HD | PPCISelLowering.cpp | 1850 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
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