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Searched refs:CTLZ (Results 1 – 24 of 24) sorted by relevance

/NextBSD/contrib/llvm/lib/Transforms/Utils/
HDIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h335 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp304 case ISD::CTLZ: return "ctlz"; in getOperationName()
HDLegalizeDAG.cpp2822 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); in ExpandBitCount()
2823 case ISD::CTLZ: { in ExpandBitCount()
2859 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount()
2862 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); in ExpandBitCount()
2884 case ISD::CTLZ: in ExpandNode()
4115 case ISD::CTLZ: in PromoteNode()
4130 } else if (Node->getOpcode() == ISD::CTLZ || in PromoteNode()
HDLegalizeVectorTypes.cpp71 case ISD::CTLZ: in ScalarizeVectorResult()
618 case ISD::CTLZ: in SplitVectorResult()
1390 case ISD::CTLZ: in SplitVectorOperand()
1993 case ISD::CTLZ: in WidenVectorResult()
HDLegalizeVectorOps.cpp282 case ISD::CTLZ: in LegalizeOp()
HDLegalizeIntegerTypes.cpp62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
1265 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
HDSelectionDAG.cpp2242 case ISD::CTLZ: in computeKnownBits()
2860 case ISD::CTLZ: in getNode()
2952 case ISD::CTLZ: in getNode()
HDDAGCombiner.cpp1355 case ISD::CTLZ: return visitCTLZ(N); in visit()
4707 if (N1C && N0.getOpcode() == ISD::CTLZ && in visitSRL()
4819 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); in visitCTLZ()
13533 TLI.isOperationLegal(ISD::CTLZ, XType))) { in SimplifySelectCC()
13534 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0); in SimplifySelectCC()
HDTargetLowering.cpp1280 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
HDSelectionDAGBuilder.cpp4672 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, in visitIntrinsicCall()
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp126 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
127 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp139 setOperationAction(ISD::CTLZ, MVT::i64, Custom); in BPFTargetLowering()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1400 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1401 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1486 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF, in HexagonTargetLowering()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp253 setOperationAction(ISD::CTLZ, MVT::i16, Legal); in NVPTXTargetLowering()
254 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in NVPTXTargetLowering()
255 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in NVPTXTargetLowering()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp230 setOperationAction(ISD::CTLZ, MVT::i32, Promote); in SystemZTargetLowering()
231 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
315 setOperationAction(ISD::CTLZ, VT, Legal); in SystemZTargetLowering()
4319 return DAG.getNode(ISD::CTLZ, SDLoc(Op), in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp262 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType()
2037 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
HDMipsISelLowering.cpp407 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in MipsTargetLowering()
409 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in MipsTargetLowering()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1479 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1534 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp292 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
368 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td391 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp714 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in ARMTargetLowering()
4333 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); in LowerCTTZ() local
4334 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ); in LowerCTTZ()
4387 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); in LowerCTTZ()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); in X86TargetLowering()
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); in X86TargetLowering()
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); in X86TargetLowering()
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); in X86TargetLowering()
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); in X86TargetLowering()
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); in X86TargetLowering()
710 setOperationAction(ISD::CTLZ, VT, Expand); in X86TargetLowering()
1442 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal); in X86TargetLowering()
1443 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal); in X86TargetLowering()
18595 case ISD::CTLZ: return LowerCTLZ(Op, DAG); in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp412 setOperationAction(ISD::CTLZ, VT, Legal); in PPCTargetLowering()
416 setOperationAction(ISD::CTLZ, VT, Expand); in PPCTargetLowering()
2252 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC()