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Searched refs:CSR_WRITE_2 (Results 1 – 25 of 68) sorted by relevance

123

/NextBSD/sys/dev/ep/
HDif_ep.c142 CSR_WRITE_2(sc, EP_W0_EEPROM_COMMAND, in ep_get_e()
404 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER); in epinit_locked()
406 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP); in epinit_locked()
410 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0); in epinit_locked()
413 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ); in epinit_locked()
419 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET); in epinit_locked()
420 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET); in epinit_locked()
429 CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff); in epinit_locked()
431 CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS); in epinit_locked()
432 CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS); in epinit_locked()
[all …]
HDif_ep_pccard.c166 CSR_WRITE_2(sc, EP_W0_ADDRESS_CFG, result & 0xc000); in ep_pccard_attach()
175 CSR_WRITE_2(sc, EP_W0_PRODUCT_ID, sc->epb.prod_id); in ep_pccard_attach()
182 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040); in ep_pccard_attach()
184 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0xc040); in ep_pccard_attach()
185 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET); in ep_pccard_attach()
186 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET); in ep_pccard_attach()
189 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040); in ep_pccard_attach()
/NextBSD/sys/dev/bm/
HDif_bm.c172 CSR_WRITE_2(sc, BM_MII_CSR, val); in bm_mii_bitbang_write()
228 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); in bm_miibus_statchg()
242 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); in bm_miibus_statchg()
916 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); in bm_setladrf()
923 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); in bm_setladrf()
929 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); in bm_setladrf()
956 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); in bm_setladrf()
957 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); in bm_setladrf()
958 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); in bm_setladrf()
959 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); in bm_setladrf()
[all …]
/NextBSD/sys/dev/vx/
HDif_vx.c163 CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET); in vx_attach()
180 CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD in vx_attach()
239 CSR_WRITE_2(sc, VX_COMMAND, RX_RESET); in vx_init_locked()
241 CSR_WRITE_2(sc, VX_COMMAND, TX_RESET); in vx_init_locked()
248 CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | in vx_init_locked()
250 CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE | in vx_init_locked()
259 CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff); in vx_init_locked()
264 CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE); in vx_init_locked()
265 CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE); in vx_init_locked()
285 CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER | in vx_setfilter()
[all …]
/NextBSD/sys/dev/sn/
HDif_sn.c276 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); in sninit_locked()
278 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); in sninit_locked()
282 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); in sninit_locked()
290 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | in sninit_locked()
296 CSR_WRITE_2(sc, CONFIG_REG_W, flags); in sninit_locked()
302 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); in sninit_locked()
325 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); in sninit_locked()
442 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); in snstart_locked()
492 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); in snstart_locked()
498 CSR_WRITE_2(sc, DATA_REG_W, 0); in snstart_locked()
[all …]
/NextBSD/sys/dev/ex/
HDif_ex.c380 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit); in ex_init_locked()
382 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe); in ex_init_locked()
383 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit); in ex_init_locked()
499 CSR_WRITE_2(sc, HOST_ADDR_REG, dest); in ex_start_locked()
500 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD); in ex_start_locked()
501 CSR_WRITE_2(sc, IO_PORT_REG, 0); in ex_start_locked()
502 CSR_WRITE_2(sc, IO_PORT_REG, next); in ex_start_locked()
503 CSR_WRITE_2(sc, IO_PORT_REG, data_len); in ex_start_locked()
534 CSR_WRITE_2(sc, HOST_ADDR_REG, in ex_start_locked()
536 CSR_WRITE_2(sc, IO_PORT_REG, dest); in ex_start_locked()
[all …]
/NextBSD/sys/dev/xl/
HDif_xl.c406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); in xl_mii_bitbang_write()
571 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
574 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
643 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); in xl_rxfilter_90x()
684 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); in xl_rxfilter_90xB()
706 CSR_WRITE_2(sc, XL_COMMAND, in xl_rxfilter_90xB()
715 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); in xl_rxfilter_90xB()
736 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); in xl_setcfg()
821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); in xl_setmode()
823 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); in xl_setmode()
[all …]
/NextBSD/sys/dev/vte/
HDif_vte.c178 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | in vte_miibus_readreg()
202 CSR_WRITE_2(sc, VTE_MMWD, val); in vte_miibus_writereg()
203 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | in vte_miibus_writereg()
259 CSR_WRITE_2(sc, VTE_MRICR, val); in vte_miibus_statchg()
267 CSR_WRITE_2(sc, VTE_MTICR, val); in vte_miibus_statchg()
1159 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); in vte_start_locked()
1255 CSR_WRITE_2(sc, VTE_MCR0, mcr); in vte_mac_config()
1356 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_intr()
1377 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); in vte_intr()
1576 CSR_WRITE_2(sc, VTE_MRDCR, prog | in vte_rxeof()
[all …]
/NextBSD/sys/dev/bwi/
HDbwimac.c217 CSR_WRITE_2(sc, data_reg, v); in bwi_memobj_write_2()
230 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16); in bwi_memobj_write_4()
234 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff); in bwi_memobj_write_4()
278 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC); in bwi_mac_lateattach()
349 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0); in bwi_mac_init()
366 CSR_WRITE_2(sc, 0x60e, 0); in bwi_mac_init()
367 CSR_WRITE_2(sc, 0x610, 0x8000); in bwi_mac_init()
368 CSR_WRITE_2(sc, 0x604, 0); in bwi_mac_init()
369 CSR_WRITE_2(sc, 0x606, 0x200); in bwi_mac_init()
393 CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay); in bwi_mac_init()
[all …]
HDbwiphy.c140 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_write()
141 CSR_WRITE_2(sc, BWI_PHY_DATA, data); in bwi_phy_write()
149 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_read()
442 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev4()
452 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev4()
489 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100); in bwi_phy_init_11b_rev4()
536 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0); in bwi_phy_init_11b_rev5()
560 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev5()
568 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev5()
722 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2); in bwi_phy_init_11b_rev6()
[all …]
HDbwirf.c201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_write()
202 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data); in bwi_rf_write()
220 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_read()
251 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO); in bwi_rf_attach()
255 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO); in bwi_rf_attach()
354 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan)); in bwi_rf_set_chan()
580 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4)); in bwi_rf_work_around()
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1)); in bwi_rf_work_around()
584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan)); in bwi_rf_work_around()
786 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f); in bwi_rf_init_bcm2050()
[all …]
/NextBSD/sys/dev/wi/
HDif_wi_pci.c154 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_pci_attach()
155 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_pci_attach()
202 CSR_WRITE_2(sc, WI_PCICOR_OFF, WI_PCICOR_RESET); in wi_pci_attach()
205 CSR_WRITE_2(sc, WI_PCICOR_OFF, 0x0000); in wi_pci_attach()
220 CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC); in wi_pci_attach()
HDif_wi.c576 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_intr()
577 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_intr()
583 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_intr()
598 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS); in wi_intr()
609 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS); in wi_enable()
684 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_stop()
1109 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_reset()
1110 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_reset()
1260 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); in wi_rx_intr()
1271 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); in wi_rx_intr()
[all …]
HDif_wi_macio.c137 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_macio_attach()
138 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_macio_attach()
HDif_wi_pccard.c195 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_pccard_attach()
196 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_pccard_attach()
/NextBSD/sys/dev/an/
HDif_an.c356 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0); in an_probe()
357 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF); in an_probe()
1221 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0); in an_intr()
1224 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS(sc->mpi350)); in an_intr()
1227 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_MIC); in an_intr()
1236 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT); in an_intr()
1241 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX); in an_intr()
1246 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_CPY); in an_intr()
1251 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX); in an_intr()
1256 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_EXC); in an_intr()
[all …]
/NextBSD/sys/dev/ste/
HDif_ste.c191 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
298 CSR_WRITE_2(sc, STE_MACCTL0, cfg); in ste_miibus_statchg()
395 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); in ste_read_eeprom()
448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); in ste_rxfilter()
449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); in ste_rxfilter()
450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); in ste_rxfilter()
451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); in ste_rxfilter()
552 CSR_WRITE_2(sc, STE_COUNTDOWN, in ste_intr()
579 CSR_WRITE_2(sc, STE_IMR, intrs); in ste_intr()
[all …]
/NextBSD/sys/dev/stge/
HDif_stge.c401 CSR_WRITE_2(sc, STGE_EepromCtrl, in stge_read_eeprom()
1315 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_ioctl()
1323 CSR_WRITE_2(sc, STGE_IntEnable, in stge_ioctl()
1512 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); in stge_intr()
2019 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); in stge_init_locked()
2020 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); in stge_init_locked()
2021 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); in stge_init_locked()
2063 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); in stge_init_locked()
2070 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); in stge_init_locked()
2095 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_init_locked()
[all …]
/NextBSD/sys/dev/vge/
HDif_vgevar.h219 #define CSR_WRITE_2(sc, reg, val) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/NextBSD/sys/dev/vr/
HDif_vr.c274 CSR_WRITE_2(sc, VR_MIIDATA, data); in vr_miibus_writereg()
729 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_attach()
730 CSR_WRITE_2(sc, VR_IMR, 0); in vr_attach()
732 CSR_WRITE_2(sc, VR_MII_IMR, 0); in vr_attach()
1608 CSR_WRITE_2(sc, VR_ISR, status); in vr_poll_locked()
1672 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_intr()
1703 CSR_WRITE_2(sc, VR_IMR, 0); in vr_int_task()
1704 CSR_WRITE_2(sc, VR_ISR, status); in vr_int_task()
1709 CSR_WRITE_2(sc, VR_ISR, status); in vr_int_task()
1735 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); in vr_int_task()
[all …]
/NextBSD/sys/dev/tl/
HDif_tl.c378 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
404 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
418 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
432 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
435 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
446 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
462 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
482 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
501 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
[all …]
/NextBSD/sys/dev/rl/
HDif_rl.c468 CSR_WRITE_2(sc, rl8139_reg, data); in rl_miibus_writereg()
1215 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof()
1326 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); in rl_twister_update()
1329 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); in rl_twister_update()
1472 CSR_WRITE_2(sc, RL_ISR, status); in rl_poll_locked()
1511 CSR_WRITE_2(sc, RL_IMR, 0); in rl_intr()
1513 CSR_WRITE_2(sc, RL_ISR, status); in rl_intr()
1537 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_intr()
1749 CSR_WRITE_2(sc, RL_IMR, 0); in rl_init_locked()
1753 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init_locked()
[all …]
/NextBSD/sys/dev/re/
HDif_re.c603 CSR_WRITE_2(sc, re8139_reg, data); in re_miibus_writereg()
811 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); in re_diag()
828 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); in re_diag()
840 CSR_WRITE_2(sc, RL_ISR, status); in re_diag()
2525 CSR_WRITE_2(sc, RL_ISR, status); in re_poll_locked()
2554 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr()
2575 CSR_WRITE_2(sc, RL_ISR, status); in re_int_task()
2628 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); in re_int_task()
2649 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr_msi()
2657 CSR_WRITE_2(sc, RL_ISR, status); in re_intr_msi()
[all …]
/NextBSD/sys/dev/msk/
HDif_msk.c687 CSR_WRITE_2(sc_if->msk_softc, in msk_rx_fill()
752 CSR_WRITE_2(sc_if->msk_softc, in msk_init_rx_ring()
820 CSR_WRITE_2(sc_if->msk_softc, in msk_init_jumbo_rx_ring()
1294 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); in msk_phy_power()
1308 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), in msk_phy_power()
1310 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), in msk_phy_power()
1367 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); in mskc_reset()
1371 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); in mskc_reset()
1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_reset()
1377 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_reset()
[all …]
/NextBSD/sys/dev/fxp/
HDif_fxp.c1146 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_shiftin()
1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1168 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_getword()
1182 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_getword()
1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1201 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_getword()
1205 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1208 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_getword()
[all …]

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