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Searched refs:BR_CC (Results 1 – 25 of 27) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp103 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in BPFTargetLowering()
174 case ISD::BR_CC: in LowerOperation()
488 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, in LowerBR_CC()
520 case BPFISD::BR_CC: in getTargetNodeName()
HDBPFISelLowering.h30 BR_CC, enumerator
HDBPFInstrInfo.td40 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h554 BR_CC, enumerator
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.h58 BR_CC, enumerator
HDMSP430ISelLowering.cpp109 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
110 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in MSP430TargetLowering()
197 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
907 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), in LowerBR_CC()
1151 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; in getTargetNodeName()
HDMSP430InstrInfo.td61 def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC,
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeDAG.cpp1230 case ISD::BR_CC: { in LegalizeOp()
1233 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; in LegalizeOp()
3891 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, in ExpandNode()
3900 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, in ExpandNode()
4023 case ISD::BR_CC: { in ExpandNode()
4042 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
4047 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, in ExpandNode()
4107 if (Node->getOpcode() == ISD::BR_CC) in PromoteNode()
4266 case ISD::BR_CC: { in PromoteNode()
4275 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), in PromoteNode()
HDSelectionDAGDumper.cpp272 case ISD::BR_CC: return "br_cc"; in getOperationName()
HDLegalizeFloatTypes.cpp690 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; in SoftenFloatOperand()
1382 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break; in ExpandFloatOperand()
HDLegalizeIntegerTypes.cpp854 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; in PromoteIntegerOperand()
2601 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; in ExpandIntegerOperand()
HDDAGCombiner.cpp1395 case ISD::BR_CC: return visitBR_CC(N); in visit()
8953 TLI.isOperationLegalOrCustom(ISD::BR_CC, in visitBRCOND()
8955 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, in visitBRCOND()
9105 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, in visitBR_CC()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp148 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in NVPTXTargetLowering()
149 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in NVPTXTargetLowering()
150 setOperationAction(ISD::BR_CC, MVT::i1, Expand); in NVPTXTargetLowering()
151 setOperationAction(ISD::BR_CC, MVT::i8, Expand); in NVPTXTargetLowering()
152 setOperationAction(ISD::BR_CC, MVT::i16, Expand); in NVPTXTargetLowering()
153 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in NVPTXTargetLowering()
154 setOperationAction(ISD::BR_CC, MVT::i64, Expand); in NVPTXTargetLowering()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1453 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1454 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1455 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1456 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1472 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
2812 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1451 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1455 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1458 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in HexagonTargetLowering()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp133 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AArch64TargetLowering()
134 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AArch64TargetLowering()
135 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in AArch64TargetLowering()
136 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in AArch64TargetLowering()
180 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in AArch64TargetLowering()
287 setOperationAction(ISD::BR_CC, MVT::f16, Promote); in AArch64TargetLowering()
355 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand); in AArch64TargetLowering()
388 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand); in AArch64TargetLowering()
543 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand); in AArch64TargetLowering()
1948 case ISD::BR_CC: in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp323 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in MipsTargetLowering()
324 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in MipsTargetLowering()
325 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in MipsTargetLowering()
326 setOperationAction(ISD::BR_CC, MVT::i64, Expand); in MipsTargetLowering()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600ISelLowering.cpp70 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in R600TargetLowering()
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in R600TargetLowering()
HDAMDGPUISelLowering.cpp242 setOperationAction(ISD::BR_CC, MVT::i1, Expand); in AMDGPUTargetLowering()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td446 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp94 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp869 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in ARMTargetLowering()
870 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in ARMTargetLowering()
871 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in ARMTargetLowering()
6567 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp295 setOperationAction(ISD::BR_CC , MVT::f32, Expand); in X86TargetLowering()
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand); in X86TargetLowering()
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand); in X86TargetLowering()
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand); in X86TargetLowering()
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand); in X86TargetLowering()
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand); in X86TargetLowering()
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand); in X86TargetLowering()
1294 setOperationAction(ISD::BR_CC, MVT::i1, Expand); in X86TargetLowering()
23385 case ISD::BR_CC: in CMPEQCombine()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp148 setOperationAction(ISD::BR_CC, VT, Custom); in SystemZTargetLowering()
4282 case ISD::BR_CC: in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelDAGToDAG.cpp2850 case ISD::BR_CC: { in Select()

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